target/riscv: Set disassemble_info::endian value in disas_set_info()
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210212931.62401-8-philmd@linaro.org>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 47424fd..6da3917 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1152,6 +1152,15 @@
CPURISCVState *env = &cpu->env;
info->target_info = &cpu->cfg;
+ /*
+ * A couple of bits in MSTATUS set the endianness:
+ * - MSTATUS_UBE (User-mode),
+ * - MSTATUS_SBE (Supervisor-mode),
+ * - MSTATUS_MBE (Machine-mode)
+ * but we don't implement that yet.
+ */
+ info->endian = BFD_ENDIAN_LITTLE;
+
switch (env->xl) {
case MXL_RV32:
info->print_insn = print_insn_riscv32;
