commit 0a476786263fd3b68b89634561576aedac49e44a
author Richard Henderson <richard.henderson@linaro.org> Sun Feb 26 12:32:01 2023 -1000
committer Richard Henderson <richard.henderson@linaro.org> Mon Mar 13 06:44:37 2023 -0700
tree c2f6831a1822e02f45a832f51a0072af16f6550f
parent 5c48ad758d959fc5db34d10096b608c6c78d6d22

target/tricore: Use setcondi instead of explicit allocation

This removes the only use of temp.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/tricore/translate.c

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 19cf4b6..6b20658 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3514,17 +3514,14 @@
 {
     uint32_t op2;
     uint32_t r1;
-    TCGv temp;
 
     r1 = MASK_OP_SR_S1D(ctx->opcode);
     op2 = MASK_OP_SR_OP2(ctx->opcode);
 
     switch (op2) {
     case OPC2_16_SR_RSUB:
-        /* overflow only if r1 = -0x80000000 */
-        temp = tcg_const_i32(-0x80000000);
-        /* calc V bit */
-        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
+        /* calc V bit -- overflow only if r1 = -0x80000000 */
+        tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
         tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
         /* calc SV bit */
         tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);