commit 095fe72a128b34d4f9317c2798c6fa7762a9e3e6
author Himanshu Chauhan <hchauhan@ventanamicro.com> Thu Oct 19 12:25:46 2023 +0530
committer Alistair Francis <alistair.francis@wdc.com> Tue Nov 07 11:06:02 2023 +1000
tree 3dad05c21d2bbc5d45b8455b820ac9dbc88c393e
parent a3abecbef0ad5e121c0d3f8f26568ab0466d9a6a

Add epmp to extensions list and rename it to smepmp

Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231019065546.1431579-1-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/csr.c

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a5be1c2..f4e0a39 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -524,9 +524,9 @@
     return RISCV_EXCP_ILLEGAL_INST;
 }
 
-static RISCVException epmp(CPURISCVState *env, int csrno)
+static RISCVException smepmp(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->epmp) {
+    if (riscv_cpu_cfg(env)->ext_smepmp) {
         return RISCV_EXCP_NONE;
     }
 
@@ -4762,7 +4762,7 @@
     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
 
     /* Physical Memory Protection */
-    [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
+    [CSR_MSECCFG]    = { "mseccfg", smepmp, read_mseccfg, write_mseccfg,
                          .min_priv_ver = PRIV_VERSION_1_11_0           },
     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },