commit 08572022e5b743f7f52ed99cd1f4e50f77ff0038
author Richard Henderson <richard.henderson@linaro.org> Mon Jul 17 15:48:27 2023 +0100
committer Richard Henderson <richard.henderson@linaro.org> Mon Jul 17 15:48:48 2023 +0100
tree 5b102fdc0e98041fb4bc61a7b3d1c3e2513b6fca
parent f44ccac2c0c4c8dc8007b8647e50dcfb16fe7cce
parent c2c1c4a35c7c2b1a4140b0942b9797c857e476a4

Merge tag 'pull-target-arm-20230717' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/sbsa-ref: set 'slots' property of xhci
 * linux-user: Remove pointless NULL check in clock_adjtime handling
 * ptw: Fix S1_ptw_translate() debug path
 * ptw: Account for FEAT_RME when applying {N}SW, SA bits
 * accel/tcg: Zero-pad PC in TCG CPU exec trace lines
 * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write

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# gpg: Signature made Mon 17 Jul 2023 01:47:01 PM BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20230717' of https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
  accel/tcg: Zero-pad PC in TCG CPU exec trace lines
  target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
  target/arm: Fix S1_ptw_translate() debug path
  target/arm/ptw.c: Add comments to S1Translate struct fields
  linux-user: Remove pointless NULL check in clock_adjtime handling
  hw/arm/sbsa-ref: set 'slots' property of xhci

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>