Implement Arm BKPT instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1740 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3b36839..7cc7da6 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -34,6 +34,7 @@
#define EXCP_DATA_ABORT 4
#define EXCP_IRQ 5
#define EXCP_FIQ 6
+#define EXCP_BKPT 7
/* We currently assume float and double are IEEE single and double
precision respectively.
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 538e17a..5804df8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -127,6 +127,7 @@
offset = 0;
break;
case EXCP_PREFETCH_ABORT:
+ case EXCP_BKPT:
new_mode = ARM_CPU_MODE_ABT;
addr = 0x0c;
mask = CPSR_A | CPSR_I;
diff --git a/target-arm/op.c b/target-arm/op.c
index 35419a1..acac239 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -885,6 +885,12 @@
cpu_loop_exit();
}
+void OPPROTO op_bkpt(void)
+{
+ env->exception_index = EXCP_BKPT;
+ cpu_loop_exit();
+}
+
/* VFP support. We follow the convention used for VFP instrunctions:
Single precition routines have a "s" suffix, double precision a
"d" suffix. */
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 089fbf2..5f81708 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1217,6 +1217,12 @@
gen_op_addl_T0_T1_saturate();
gen_movl_reg_T0(s, rd);
break;
+ case 7: /* bkpt */
+ gen_op_movl_T0_im((long)s->pc - 4);
+ gen_op_movl_reg_TN[0][15]();
+ gen_op_bkpt();
+ s->is_jmp = DISAS_JUMP;
+ break;
case 0x8: /* signed multiply */
case 0xa:
case 0xc:
@@ -2183,6 +2189,13 @@
gen_bx(s);
break;
+ case 0xe: /* bkpt */
+ gen_op_movl_T0_im((long)s->pc - 2);
+ gen_op_movl_reg_TN[0][15]();
+ gen_op_bkpt();
+ s->is_jmp = DISAS_JUMP;
+ break;
+
default:
goto undef;
}