| commit | 9b113a09ff34857d463c130faa873c7b6fc4a004 | [log] [tgz] |
|---|---|---|
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | Tue Jun 18 16:22:21 2024 +0100 |
| committer | Peter Maydell <peter.maydell@linaro.org> | Fri Jun 21 14:01:58 2024 +0100 |
| tree | 04cf73d4107a855c699624eca5cc2c85a36aa8e0 | |
| parent | 7175a562f157d39725ab396e39c1e8e410d206b3 [diff] |
hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
Fix the system bus interrupt line to CPU core assignment.
Fixes: ddcf58e044ce0 ("hw/arm/xilinx_zynq: Support up to two CPU cores")
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240610052906.4432-1-sebastian.huber@embedded-brains.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>