)]}'
{
  "commit": "055f9cb47d4e1c5889bdbca4e6dc1d5201964ccb",
  "tree": "e43e2e94a6bb9dcac1d2205dbbb0cb5c91e5417c",
  "parents": [
    "883a4d4da4ded9844c7d398e81f7c87e2716cb9d"
  ],
  "author": {
    "name": "Abhigyan Kumar",
    "email": "314abh@gmail.com",
    "time": "Thu Jul 30 04:30:28 2026 +0530"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Fri Sep 04 09:41:58 2026 +1000"
  },
  "message": "target/riscv: prevent abrupt abortion on unassigned value write to tdata\n\ntdata_csr_write is approachable by guest programs. In case of unassigned\nvalues written to a tdata CSR in debug mode, the switch-case falls\nthrough straight to default causing an immediate abort. The risc-v spec\nsays:\n\n    All tdata registers follow write-any-read-legal semantics. If a debugger\n    writes an unsupported configuration, the register will read back a value\n    that is supported (which may simply be a disabled trigger). This means\n    that a debugger must always read back values it writes to tdata\n    registers, unless it already knows what is supported.\n\nThis fix correctly ensures that the WARL behaviour of tdata CSRs.\n\nFixes: a42bd001 (\"target/riscv: debug: Determine the trigger type from\ntdata1.type\")\nSigned-off-by: Abhigyan Kumar \u003c314abh@gmail.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20260729230028.1797355-1-314abh@gmail.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "148201f3cb178df821d88d71e3eb86899f04f953",
      "old_mode": 33188,
      "old_path": "target/riscv/tcg/debug.c",
      "new_id": "e4d719a1da93bae8dbbf6dfeaf18b5e5e231d25d",
      "new_mode": 33188,
      "new_path": "target/riscv/tcg/debug.c"
    }
  ]
}