commit 015fc6fcdb90034a7551091f8cd9a47ca1bd26b1
author Richard Henderson <richard.henderson@linaro.org> Sat Nov 04 12:33:08 2023 -0700
committer Richard Henderson <richard.henderson@linaro.org> Wed Jun 05 09:05:10 2024 -0700
tree 7f919d8af7e4eafc28e8639288f1e9f3d2ac85c4
parent 3335a04806d337c69f44a707cdc27515d6c91d84

target/sparc: Implement ADDXC, ADDXCcc

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/sparc/insns.decode

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 056fba9..5d1c55a 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -376,6 +376,9 @@
     ARRAY16     10 ..... 110110 ..... 0 0001 0010 .....    @r_r_r
     ARRAY32     10 ..... 110110 ..... 0 0001 0100 .....    @r_r_r
 
+    ADDXC       10 ..... 110110 ..... 0 0001 0001 .....    @r_r_r
+    ADDXCcc     10 ..... 110110 ..... 0 0001 0011 .....    @r_r_r
+
     ALIGNADDR   10 ..... 110110 ..... 0 0001 1000 .....    @r_r_r
     ALIGNADDRL  10 ..... 110110 ..... 0 0001 1010 .....    @r_r_r
 

target/sparc/translate.c

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 59b922c..ad12486 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -433,6 +433,17 @@
     gen_op_addcc_int(dst, src1, src2, gen_carry32());
 }
 
+static void gen_op_addxc(TCGv dst, TCGv src1, TCGv src2)
+{
+    tcg_gen_add_tl(dst, src1, src2);
+    tcg_gen_add_tl(dst, dst, cpu_cc_C);
+}
+
+static void gen_op_addxccc(TCGv dst, TCGv src1, TCGv src2)
+{
+    gen_op_addcc_int(dst, src1, src2, cpu_cc_C);
+}
+
 static void gen_op_subcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin)
 {
     TCGv z = tcg_constant_tl(0);
@@ -3692,6 +3703,9 @@
 TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16)
 TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32)
 
+TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc)
+TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc)
+
 static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2)
 {
 #ifdef TARGET_SPARC64