commit | 3335a04806d337c69f44a707cdc27515d6c91d84 | [log] [tgz] |
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author | Richard Henderson <richard.henderson@linaro.org> | Sat Nov 04 12:21:37 2023 -0700 |
committer | Richard Henderson <richard.henderson@linaro.org> | Wed Jun 05 09:05:10 2024 -0700 |
tree | f9fbfc1d70e2d389023f715b7b33f2a56f0f89f7 | |
parent | 4fd71d19acd6e05b74927a0b5c4a5b0650e3d6f5 [diff] |
target/sparc: Add feature bits for VIS 3 The manual separates VIS 3 and VIS 3B, even though they are both present in all extant cpus. For clarity, let the translator match the manual but otherwise leave them on the same feature bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>