xilinx: Convert most xilinx devices to MemoryRegion
This converts ethlite, intc, timer and uartlite to use
MemoryRegions.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
diff --git a/hw/xilinx_ethlite.c b/hw/xilinx_ethlite.c
index f35ba84..6f44c84 100644
--- a/hw/xilinx_ethlite.c
+++ b/hw/xilinx_ethlite.c
@@ -50,6 +50,7 @@
struct xlx_ethlite
{
SysBusDevice busdev;
+ MemoryRegion mmio;
qemu_irq irq;
NICState *nic;
NICConf conf;
@@ -70,7 +71,8 @@
}
}
-static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct xlx_ethlite *s = opaque;
uint32_t r = 0;
@@ -98,10 +100,12 @@
}
static void
-eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+eth_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
+ uint32_t value = val64;
addr >>= 2;
switch (addr)
@@ -146,12 +150,14 @@
}
}
-static CPUReadMemoryFunc * const eth_read[] = {
- NULL, NULL, ð_readl,
-};
-
-static CPUWriteMemoryFunc * const eth_write[] = {
- NULL, NULL, ð_writel,
+static const MemoryRegionOps eth_ops = {
+ .read = eth_read,
+ .write = eth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
};
static int eth_can_rx(VLANClientState *nc)
@@ -206,13 +212,12 @@
static int xilinx_ethlite_init(SysBusDevice *dev)
{
struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
- int regs;
sysbus_init_irq(dev, &s->irq);
s->rxbuf = 0;
- regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, regs);
+ memory_region_init_io(&s->mmio, ð_ops, s, "xilinx-ethlite", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &s->mmio);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c
index cb72d5a..58b73d9 100644
--- a/hw/xilinx_intc.c
+++ b/hw/xilinx_intc.c
@@ -40,6 +40,7 @@
struct xlx_pic
{
SysBusDevice busdev;
+ MemoryRegion mmio;
qemu_irq parent_irq;
/* Configuration reg chosen at synthesis-time. QEMU populates
@@ -72,7 +73,8 @@
}
}
-static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t r = 0;
@@ -91,9 +93,11 @@
}
static void
-pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+pic_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
+ uint32_t value = val64;
addr >>= 2;
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
@@ -116,14 +120,14 @@
update_irq(p);
}
-static CPUReadMemoryFunc * const pic_read[] = {
- NULL, NULL,
- &pic_readl,
-};
-
-static CPUWriteMemoryFunc * const pic_write[] = {
- NULL, NULL,
- &pic_writel,
+static const MemoryRegionOps pic_ops = {
+ .read = pic_read,
+ .write = pic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
};
static void irq_handler(void *opaque, int irq, int level)
@@ -148,13 +152,12 @@
static int xilinx_intc_init(SysBusDevice *dev)
{
struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
- int pic_regs;
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &p->parent_irq);
- pic_regs = cpu_register_io_memory(pic_read, pic_write, p, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, pic_regs);
+ memory_region_init_io(&p->mmio, &pic_ops, p, "xilinx-pic", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &p->mmio);
return 0;
}
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index f1c7abc..8779c56 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -59,6 +59,7 @@
struct timerblock
{
SysBusDevice busdev;
+ MemoryRegion mmio;
qemu_irq irq;
uint32_t nr_timers;
uint32_t freq_hz;
@@ -85,7 +86,8 @@
qemu_set_irq(t->irq, !!irq);
}
-static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
@@ -134,11 +136,13 @@
}
static void
-timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+timer_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
unsigned int timer;
+ uint32_t value = val64;
addr >>= 2;
timer = timer_from_addr(addr);
@@ -166,14 +170,14 @@
timer_update_irq(t);
}
-static CPUReadMemoryFunc * const timer_read[] = {
- NULL, NULL,
- &timer_readl,
-};
-
-static CPUWriteMemoryFunc * const timer_write[] = {
- NULL, NULL,
- &timer_writel,
+static const MemoryRegionOps timer_ops = {
+ .read = timer_read,
+ .write = timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
};
static void timer_hit(void *opaque)
@@ -192,7 +196,6 @@
{
struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
unsigned int i;
- int timer_regs;
/* All timers share a single irq line. */
sysbus_init_irq(dev, &t->irq);
@@ -209,9 +212,9 @@
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
- timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
+ memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
+ R_MAX * 4 * t->nr_timers);
+ sysbus_init_mmio_region(dev, &t->mmio);
return 0;
}
diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index 467a26c..ceb7b4d 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -49,6 +49,7 @@
struct xlx_uartlite
{
SysBusDevice busdev;
+ MemoryRegion mmio;
CharDriverState *chr;
qemu_irq irq;
@@ -82,7 +83,8 @@
s->regs[R_STATUS] = r;
}
-static uint32_t uart_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t
+uart_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
struct xlx_uartlite *s = opaque;
uint32_t r = 0;
@@ -107,9 +109,11 @@
}
static void
-uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+uart_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
{
struct xlx_uartlite *s = opaque;
+ uint32_t value = val64;
unsigned char ch = value;
addr >>= 2;
@@ -147,16 +151,14 @@
uart_update_irq(s);
}
-static CPUReadMemoryFunc * const uart_read[] = {
- &uart_readl,
- &uart_readl,
- &uart_readl,
-};
-
-static CPUWriteMemoryFunc * const uart_write[] = {
- &uart_writel,
- &uart_writel,
- &uart_writel,
+static const MemoryRegionOps uart_ops = {
+ .read = uart_read,
+ .write = uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
@@ -196,14 +198,12 @@
static int xilinx_uartlite_init(SysBusDevice *dev)
{
struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
- int uart_regs;
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
- uart_regs = cpu_register_io_memory(uart_read, uart_write, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
+ memory_region_init_io(&s->mmio, &uart_ops, s, "xilinx-uartlite", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &s->mmio);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr)
