)]}' { "log": [ { "commit": "79e63bc8348df12835b5c264144e50d45abe72c8", "tree": "74518151544e1dfc778ad711d511fd8d21bc298d", "parents": [ "c0d0dd02b186c12376137c5c3db8e5d0653e450e" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 23 10:53:39 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue May 12 09:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Add support for registering MSI handlers\n\nSome of the drivers (such as APLIC) require capability to registers\nMSI handlers from the parent interrupt controller (such as IMSIC)\nso add sbi_irqchip_register_msi_handler() for this purpose.\n\nLink: https://lore.kernel.org/r/20260423052339.356900-7-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "c0d0dd02b186c12376137c5c3db8e5d0653e450e", "tree": "83051bf4c1c7b122aeff48962d90f3ce32ad7ddc", "parents": [ "d861447b0b0297db5fbe28878f8568a93fcfa965" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 23 10:53:38 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue May 12 09:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Allow setting hardware interrupt affinity\n\nThe irqchip drivers can provide mechanism to set interrupt affinity\nso add hwirq_set_affinity() callback for irqchip drivers and use it\nto implement sbi_irqchip_set_affinity() which can be used by other\ndrivers.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260423052339.356900-6-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "d861447b0b0297db5fbe28878f8568a93fcfa965", "tree": "c4337e0d785550676ff63da8d2cd6e350bbf9683", "parents": [ "adb4caf765cc977c8de6534d0bf77df9dd243e41" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 23 10:53:37 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue May 12 09:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Allow marking hardware interrupts as reserved\n\nSome of the hardware interrupts may be special so allow irqchip\ndrivers to make these hardware interrupts as reserved. Introduce\nsbi_irqchip_register_reserved() for this purpose.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "adb4caf765cc977c8de6534d0bf77df9dd243e41", "tree": "52e994b87de18b628676c605cb5b42a1d1aae139", "parents": [ "255df5d8022ada847e81bc68a81e0828e693f6ba" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 23 10:53:36 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue May 12 09:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Allow interrupt client to specify line sensing\n\nThe interrupt client should be allowed to specify the line sensing\ntype of the hwirqs for which it is registering handler. To support\nthis, add hwirq_flags parameter to hwirq_setup() callback provided\nby the irqchip driver.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "255df5d8022ada847e81bc68a81e0828e693f6ba", "tree": "761e4ac2b249d03d7e519bc582b7dbf2091bc6ae", "parents": [ "0d81a78ec54be2f7c62906b1aa945240ce519c6b" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 23 10:53:35 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue May 12 09:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Keep the handler list in sorted order for irqchip\n\nLet\u0027s keep the handler list in sorted order for irqchip so that\nit is easier to allocate unused hardware interrupts based on the\nsorted list.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260423052339.356900-3-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "0d81a78ec54be2f7c62906b1aa945240ce519c6b", "tree": "6367e6ee9df90d4074b9215468d64c7fac6f830a", "parents": [ "9595829a336793744f56b978b2651350d0a1723b" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 23 10:53:34 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue May 12 09:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Check full range for existing handlers in sbi_irqchip_register_handler()\n\nCurrently, the sbi_irqchip_register_handler() only checks the first and the\nlast hardware interrupt for existing handlers which is buggy because there\nmay be existing handlers between the first and the last hardware interrupt.\n\nFixes: 0ab0c470d588 (\"lib: sbi_irqchip: Allow registering interrupt handlers\")\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260423052339.356900-2-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "9595829a336793744f56b978b2651350d0a1723b", "tree": "1bdcf69b69f986b985e3d5342e9f216498fcb354", "parents": [ "d9637d00bf47a3cc17306fc62e71652c8a83c289" ], "author": { "name": "Takumi Hara", "email": "takumihara1226@gmail.com", "time": "Thu Mar 19 22:22:32 2026 +0900" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 19:42:38 2026 +0530" }, "message": "lib: sbi_domain: reject overflowing address range in check_addr_range()\n\nsbi_domain_check_addr_range() computes `max \u003d addr + size` without\nchecking for integer overflow. When a caller passes a size large enough\nto wrap around (e.g. addr\u003d0x80000000, size\u003d0xFFFFFFFF80000000), max\nbecomes less than addr, causing the while(addr \u003c max) validation loop\nto be skipped entirely. The function then returns true without\nperforming any permission checks.\n\nThis allows an S-mode caller to bypass domain memory protection and\naccess M-mode memory through SBI extensions that use address range\nvalidation (e.g. DBCN console write/read).\n\nAdd an overflow check after computing max: if size is non-zero and\nmax wrapped to a value \u003c\u003d addr, reject the request.\n\nSigned-off-by: Takumi Hara \u003ctakumihara1226@gmail.com\u003e\nReviewed-by: Rahul Pathak \u003crahul@summations.net\u003e\nLink: https://lore.kernel.org/r/20260319132232.51572-1-takumihara1226@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "d9637d00bf47a3cc17306fc62e71652c8a83c289", "tree": "f538b6cc8936af974bf0ced3ec52f4ee9364c5a1", "parents": [ "b10e18ec854a80e938a1fc8cf23beb8f8577cbaf" ], "author": { "name": "Aurelien Jarno", "email": "aurelien@aurel32.net", "time": "Sun Apr 19 16:49:20 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 19:21:31 2026 +0530" }, "message": "lib: utils/reset: add SpacemiT P1 PMIC support\n\nThe SpacemiT P1 is a PMIC commonly found with SpacemiT CPU like K1. Add\na reset driver for it.\n\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\nTested-by: Anand Moon \u003clinux.amoon@gmail.com\u003e\nLink: https://lore.kernel.org/r/20260419150857.2705843-3-aurelien@aurel32.net\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b10e18ec854a80e938a1fc8cf23beb8f8577cbaf", "tree": "e14cf5c9f68088504138beb0ba1b13f164ee83a2", "parents": [ "5f13f9e13f8a8c08e5339cd0cf590282ef6a39a4" ], "author": { "name": "Aurelien Jarno", "email": "aurelien@aurel32.net", "time": "Sun Apr 19 16:49:19 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 19:21:31 2026 +0530" }, "message": "lib: utils/i2c: add minimal SpacemiT I2C driver\n\nAdd a simple SpacemiT I2C driver for basic byte transfers over the I2C\nbus, prioritizing simplicity over performance. The driver operates in\nPIO mode and does not use interrupts, FIFO, or DMA.\n\nThe controller is reset at the start of each transaction to ensure a\nknown initial state, regardless of prior configuration by the kernel.\nThis also avoids the need for additional error recovery code.\n\nThis will be used for communication with onboard PMIC to reset and\npower-off the board.\n\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\nTested-by: Anand Moon \u003clinux.amoon@gmail.com\u003e\nLink: https://lore.kernel.org/r/20260419150857.2705843-2-aurelien@aurel32.net\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "5f13f9e13f8a8c08e5339cd0cf590282ef6a39a4", "tree": "aa7ba457f68690ff53d26e35995109b4e0a566d5", "parents": [ "8536a351fd3af50e5eba571e562a33247b99870d" ], "author": { "name": "Andrew Jones", "email": "andrew.jones@oss.qualcomm.com", "time": "Wed Apr 01 17:08:45 2026 -0500" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 19:16:20 2026 +0530" }, "message": "lib: sbi: Fix hw a/d updating defaults\n\nThe Svade dt-binding description states that Svadu should only\nbe enabled at boot time when only Svadu is present in the DT.\nEnsure that\u0027s the case. Also, when only Svadu is supported,\ndisable FWFT.PTE_AD_HW_UPDATING, as we need both to support\ntoggling.\n\nSigned-off-by: Andrew Jones \u003candrew.jones@oss.qualcomm.com\u003e\nReviewed-by: Radim Krčmář \u003cradim.krcmar@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260401220845.190680-1-andrew.jones@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "8536a351fd3af50e5eba571e562a33247b99870d", "tree": "031e267432fd5da819e88e25e17e8fc4ccfcbc97", "parents": [ "65bb705f7b59d8f2a5683160f31db15b4e2c64d7" ], "author": { "name": "David E. Garcia Porras", "email": "david.garcia@aheadcomputing.com", "time": "Fri Apr 03 14:29:03 2026 -0600" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 11:49:59 2026 +0530" }, "message": "lib: utils/regmap: Fix reg_stride calculation in syscon regmap\n\nThe reg_stride field represents the address stride in bytes between\nconsecutive registers. The Linux kernel regmap framework validates\nregister accesses using IS_ALIGNED(reg, map-\u003ereg_stride) as an address\nalignment check (drivers/base/regmap/regmap.c). The Linux kernel syscon\ndriver (drivers/mfd/syscon.c) sets reg_stride directly to reg_io_width:\n\n syscon_config.reg_stride \u003d reg_io_width;\n\nThe current OpenSBI code incorrectly multiplies reg_io_width by 8,\nconverting a byte value to bits. Fix this by using reg_io_width directly\nas the stride value, consistent with the Linux kernel.\n\nFixes: f21d8f7d5911 (\"lib: utils/regmap: Add simple FDT based syscon regmap driver\")\nSigned-off-by: David E. Garcia Porras \u003cdavid.garcia@aheadcomputing.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260403202903.3407945-1-david.garcia@aheadcomputing.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "65bb705f7b59d8f2a5683160f31db15b4e2c64d7", "tree": "e60b4a558b4240e00a40c79eab3f716794bd612b", "parents": [ "3d8f1f386479219c4236b5c0fe483442c1bc7461" ], "author": { "name": "Michael Ellerman", "email": "mpe@kernel.org", "time": "Tue Mar 24 23:29:20 2026 +1100" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 11:30:22 2026 +0530" }, "message": "lib/sbi_pmu: Don\u0027t fallback to fixed counters when sscofpmf \u0026\u0026 !smcntrpmf\n\nCurrently when searching for a hardware counter for an event, if no\nprogrammable counter is available, the code falls back to using a fixed\ncounter (mcycle/minstret) if one matches the event.\n\nHowever the fallback is incorrect when sscofpmf is present but\nsmcntrpmf is not. That\u0027s because with sscofpmf, programmable counters\nsupport mode filtering, but the fixed counters do not (without\nsmcntrpmf). Even if the caller didn\u0027t configure mode filtering, by\ndefault programmable counters don\u0027t count M mode when sscofpmf is\npresent, whereas mcycle/minstret do.\n\nFix the logic to not fallback to a fixed counter if sscofpmf is present\nbut smcntrpmf is not.\n\nFixes: 0c304b661965 (\"lib: sbi: Allow programmable counters to monitor cycle/instret events\")\nSigned-off-by: Michael Ellerman \u003cmpe@kernel.org\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260324-mcycle-fix-v1-1-1444e9fe5c32@kernel.org\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "3d8f1f386479219c4236b5c0fe483442c1bc7461", "tree": "ec282cacbd527a2ecde71bcc8443788d3d66b0be", "parents": [ "8cd279e321ce8eedd2750d3e2ed9a906e43e6e38" ], "author": { "name": "Zhang RunMin", "email": "runmin.zhang@ingenic.com", "time": "Thu Mar 19 20:56:24 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 10:26:36 2026 +0530" }, "message": "docs: platform: update qemu_virt.md\n\nWhen using GDB for debugging, if FW_TEXT_START is not set to 0x80000000\nduring compilation, the following error occurs:\n\nReading symbols from build/platform/generic/firmware/fw_payload.elf...\nRemote debugging using localhost:1234\nmips_warm_boot ()\n at /home/zrmin/opensbi/platform/generic/mips/mips_warm_boot.S:11\n11 j _start_warm\n(gdb) b _start\nBreakpoint 1 at 0x0: file /home/zrmin/opensbi/firmware/fw_base.S, line 50.\n(gdb) c\nContinuing.\nRemote connection closed\n(gdb)\n\nWith FW_TEXT_START\u003d0x80000000, debugging works correctly:\nReading symbols from build/platform/generic/firmware/fw_payload.elf...\nRemote debugging using localhost:1234\n0x0000000000001000 in ?? ()\n(gdb) b _start\nBreakpoint 1 at 0x80000000: file /home/zrmin/opensbi/firmware/fw_base.S, line 50.\n(gdb) c\nContinuing.\n\nBreakpoint 1, _start () at /home/zrmin/opensbi/firmware/fw_base.S:50\n50 MOV_3R s0, a0, s1, a1, s2, a2\n(gdb)\n\nThis is because QEMU loads OpenSBI at address 0x80000000. When\nFW_TEXT_START does not match this address, the debug symbols are\nincorrectly offset, causing GDB to fail to set breakpoints properly.\n\nSigned-off-by: Zhang RunMin \u003crunmin.zhang@ingenic.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260319125641.480161-1-runmin.zhang@ingenic.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "8cd279e321ce8eedd2750d3e2ed9a906e43e6e38", "tree": "5d3e26492643365fa0fdadf9d056d12ad19a37a6", "parents": [ "ae8f28a868513a76e0934dbd2a0a852c295c7051" ], "author": { "name": "Yu-Chien Peter Lin", "email": "peter.lin@sifive.com", "time": "Fri Mar 27 13:49:36 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 10:11:06 2026 +0530" }, "message": "lib: fdt_domain: Default boot-hart to coldboot HART for multi-domain boot\n\nWhen \"boot-hart\" is not specified, dom-\u003eboot_hartid was left as -1U,\ncausing domain context switching to fail. Default it to the coldboot\nHART to enable SMP boot in multi-domain setups, consistent with how\nnext-arg1 is handled.\n\nAlso update its description in domain_support.md.\n\nSigned-off-by: Yu-Chien Peter Lin \u003cpeter.lin@sifive.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260327054936.3462935-1-peter.lin@sifive.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ae8f28a868513a76e0934dbd2a0a852c295c7051", "tree": "9e185c5a62dd46550878a29a89c12b2561ff315d", "parents": [ "6767861c484d07f180f3dd710b5dc59f0c525374" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Sat May 09 21:48:49 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon May 11 10:08:55 2026 +0530" }, "message": "lib: utils: Fix LLVM compile error in MPXY client driver for RPMI MM\n\nThe following compile error is seen with LLVM compiler:\n\n CC platform/generic/lib/utils/mpxy/fdt_mpxy_rpmi_mm.o\nlib/utils/mpxy/fdt_mpxy_rpmi_mm.c:17:6: error: use of GNU \u0027missing \u003d\u0027 extension in\n designator [-Werror,-Wgnu-designator]\n 17 | [0] {\n | ^\n | \u003d\nlib/utils/mpxy/fdt_mpxy_rpmi_mm.c:24:6: error: use of GNU \u0027missing \u003d\u0027 extension in\n designator [-Werror,-Wgnu-designator]\n 24 | [1] {\n | ^\n | \u003d\n2 errors generated.\n\nAdd missing \"\u003d\" in mm_srvcdata[] array initialization to address\nthe above issue.\n\nFixes: 0b041e58c078 (\"lib: utils: Add MPXY client driver for RPMI MM service group\")\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nReviewed-by: Ranbir Singh \u003cranbir.singh@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260509161849.2935816-1-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "6767861c484d07f180f3dd710b5dc59f0c525374", "tree": "28afe2faf8b0286bcba5c0800fb2e33ed1940f27", "parents": [ "1932ee3f0ae2f200431c20018e2d75dbceb65695" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Fri Apr 24 16:25:19 2026 +1000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 20:57:50 2026 +0530" }, "message": "platform: generic: Tenstorrent Atlantis support\n\nAdd the Tenstorrent Atlantis as a generic-platform. This initial support\nenables the single_fw_region option, and verifies and prints HART PMA\nCSR configuration.\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260424062520.238403-1-npiggin@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "1932ee3f0ae2f200431c20018e2d75dbceb65695", "tree": "6ee68e4c69561126cd7ce2e37c5ac63a2f2b8f5a", "parents": [ "b7fa8a246cba80d74c0993dd0275b3c1589ef8b6" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Sat Apr 25 16:10:48 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 13:16:07 2026 +0530" }, "message": "lib: sbi_timer: Introduce sbi_timer_compute_delta() and friends\n\nThe users of timer event have to compute next_event (aka timer value\nin the future) based on desired units and unit frequency. Introduce\nsbi_timer_compute_delta() and friends to simplify computing next_event\nfor timer event users.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nReviewed-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nLink: https://lore.kernel.org/r/20260425104048.2335262-5-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b7fa8a246cba80d74c0993dd0275b3c1589ef8b6", "tree": "6e17b11e6c60b1a48c1d12704428ac4f8f65abc1", "parents": [ "357fae4820718f633abeb7aa6ca00fd57a574d8d" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Sat Apr 25 16:10:47 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 13:16:05 2026 +0530" }, "message": "lib: sbi_timer: Add support for timer events\n\nCurrently, the sbi_timer only supports timer events configured via\nSBI calls. Introduce struct sbi_timer_event and related functions\nto allow configuring timer events from any part of OpenSBI.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nReviewed-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nLink: https://lore.kernel.org/r/20260425104048.2335262-4-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "357fae4820718f633abeb7aa6ca00fd57a574d8d", "tree": "a2f74446d07695af611a1ce468ebf0a5d5262fd1", "parents": [ "d8c7dc9cb038369b1ac92d3306476df6375e3037" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Sat Apr 25 16:10:46 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 13:15:43 2026 +0530" }, "message": "lib: sbi_timer: Introduce per-HART timer state\n\nCurrently, only time_delta is per-HART so introduce per-HART timer\nstate for having more per-HART timer information.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nReviewed-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nLink: https://lore.kernel.org/r/20260425104048.2335262-3-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "d8c7dc9cb038369b1ac92d3306476df6375e3037", "tree": "fb80dbb18d50063fd8358d37a3317bd74811a3c7", "parents": [ "f34cf05347325515527ea9fdb658cf8063354aea" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Sat Apr 25 16:10:45 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 13:11:13 2026 +0530" }, "message": "include: sbi: Add sbi_scratch_hartindex() macro\n\nAdd helper macro to extract hart index from scratch pointer. This\ncan be used to check whether scratch pointer belongs to a particular\nhart or not.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nReviewed-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nLink: https://lore.kernel.org/r/20260425104048.2335262-2-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "f34cf05347325515527ea9fdb658cf8063354aea", "tree": "45160a20f4f4fc42904b84e99ce5ed3fa5b33614", "parents": [ "2d211fe6f9d511cdcce344f1c9c422fe33b5a957" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Thu Apr 09 10:23:10 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 13:05:51 2026 +0530" }, "message": "platform: Remove kendryte/k210 platform\n\nThe kendryte/k210 platform does not have MMU support in S-mode hence\nonly NOMMU kernel which runs in M-mode can be used on this platform.\n\nAs of now, there is no clear use-case of supporting OpenSBI for\nkendryte/k210 platform.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260409045310.2045739-1-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2d211fe6f9d511cdcce344f1c9c422fe33b5a957", "tree": "2cfbc4ff22633ccc88fc28d0fcd5d2595bac585d", "parents": [ "0cfd6c0b5ec0f7394c4537c288a948c49894dcc6" ], "author": { "name": "Evgeny Voevodin", "email": "evvoevod@tenstorrent.com", "time": "Thu May 07 18:08:07 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 12:59:43 2026 +0530" }, "message": "lib: sbi: hart: Detect and enable Smrnmi before trap-based feature detection\n\nThe location of the RNMI/E trap vectors in the Smrnmi extension is\nimplementation-defined, so platforms with vendor-specific NMI vector\nmechanisms must install the firmware\u0027s NMI entry points themselves.\n\nAdd an smrnmi_handlers_init() callback to sbi_platform_operations that\nreceives the firmware entry points and lets platform code install them\nat the hardware-specific vector locations. Two pointers are passed:\n\n - _trap_rnmi_handler: the dedicated RNMI entry point that saves\n context using the Smrnmi MN* CSRs and returns via mnret.\n - _trap_handler: the regular M-mode trap entry since RNME is taken\n as a regular M-mode trap with NMIE\u003d0.\n\nWhen Smrnmi is present, install the platform\u0027s NMI vectors via the new\ncallback, initialize MNSCRATCH with the per-hart scratch pointer, and\nset MNSTATUS.NMIE.\n\nSmrnmi-enabled platforms must register smrnmi_handlers_init; if the\nextension is detected but no callback is registered, sbi_panic() is\ncalled since enabling NMIs without handlers in place would route\nsubsequent traps into nowhere.\n\nSigned-off-by: Evgeny Voevodin \u003cevvoevod@tenstorrent.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/88b1470e1e3348d454b4b995a11a85c01914f7af.1778176768.git.evvoevod@tenstorrent.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "0cfd6c0b5ec0f7394c4537c288a948c49894dcc6", "tree": "a9ae3f905e8d435dd91e29089192bc21fdec4ceb", "parents": [ "882b8b081c05516d40eb2e3727721469deff3ee6" ], "author": { "name": "Evgeny Voevodin", "email": "evvoevod@tenstorrent.com", "time": "Thu May 07 18:08:06 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 12:59:43 2026 +0530" }, "message": "lib: sbi: Move Zkr entropy initialization from fw_base.S to init_coldboot\n\nCurrent placement of entropy initialization via Zkr extension requires a\ntrap-based mechanism to handle absent Zkr extension case. In presence of\nSmrnmi extension no trap-based mechanisms should be used before Smrnmi is\ndetected and enabled otherwise trap will jump to undefined location.\nMove stack guard initialization into init_coldboot function body after\ndevice tree has been parsed so we know if Zkr extension is implemented by\nthe platform which helps to avoid trap-based discovery.\ninit_coldboot() is a safe place to initialize entropy because it doesn\u0027t\nreturn so no check of __stack_chk_guard against value on entry\nwill be done.\n\nSigned-off-by: Evgeny Voevodin \u003cevvoevod@tenstorrent.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/acd52b0f3468758bc5f09e6a45662341b31d4d87.1778176768.git.evvoevod@tenstorrent.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "882b8b081c05516d40eb2e3727721469deff3ee6", "tree": "44be57ad86c7f82d31387c6277f9f8deadadb77d", "parents": [ "00fec20b4976c756ddacedef23a6bf510fa00dad" ], "author": { "name": "Evgeny Voevodin", "email": "evvoevod@tenstorrent.com", "time": "Thu May 07 18:08:05 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 12:59:43 2026 +0530" }, "message": "lib: sbi: hart: Move device tree features detection before trap-based checks\n\nSmrnmi detection and enablement in the following commits will happen\nbefore any trap-based mechanism. As it relies on device tree, move\nsbi_platform_extensions_init() to the beginning of hart_detect_features().\n\nSigned-off-by: Evgeny Voevodin \u003cevvoevod@tenstorrent.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/d066935990f12e1f4f21cd709eb20afba618b134.1778176768.git.evvoevod@tenstorrent.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "00fec20b4976c756ddacedef23a6bf510fa00dad", "tree": "5fbd16c626e7755dc06e5f66ac5e4ad91ed7e8da", "parents": [ "b63606f98180cb92cc7c47c42b63bf92a21dfdee" ], "author": { "name": "Evgeny Voevodin", "email": "evvoevod@tenstorrent.com", "time": "Thu May 07 18:08:04 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 12:59:43 2026 +0530" }, "message": "firmware: Add RNMI handler infrastructure\n\nImplement basic Resumable NMI (RNMI) handler support for the RISC-V\nSmrnmi extension.\n\nThe new _trap_rnmi_handler assembly entry point saves context using the\nSmrnmi MN* CSRs (MNSCRATCH, MNEPC, MNSTATUS, MNCAUSE) and returns via\nmnret. It dispatches to sbi_trap_rnmi_handler(), which optionally calls\na platform-specific ops-\u003ernmi_handler callback for actual NMI\nprocessing. If no platform handler is registered or it fails, the\nevent is reported as an unhandled NMI.\n\nThe RNMI handler reuses the generic trap context structure but stores MN*\nCSR values (MNEPC, MNSTATUS, MNCAUSE) into the corresponding generic\nfields (mepc, mstatus, cause) for compatibility with existing trap\ninfrastructure.\n\nSigned-off-by: Evgeny Voevodin \u003cevvoevod@tenstorrent.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/050ae6d2762ba8d5b9dfb3cc1960a23aa3d6c549.1778176768.git.evvoevod@tenstorrent.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b63606f98180cb92cc7c47c42b63bf92a21dfdee", "tree": "37d67109b474509e9fce3f861eae0ff8b04355b9", "parents": [ "5d248a013281ea80be3375cfc19e8ca541d33c34" ], "author": { "name": "Evgeny Voevodin", "email": "evvoevod@tenstorrent.com", "time": "Thu May 07 18:08:03 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 12:59:43 2026 +0530" }, "message": "lib: sbi: Add Smrnmi extension macros for registers and bits\n\nAdd CSR definitions (MNSCRATCH, MNSTATUS, MNEPC, MNCAUSE) and bit definitions\n(MNSTATUS_NMIE, MNSTATUS_MNPV, MNSTATUS_MNPP). Also add SBI_HART_EXT_SMRNMI to\nthe hart extension enumeration.\n\nSigned-off-by: Evgeny Voevodin \u003cevvoevod@tenstorrent.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/1c6feb6d359b9827b3c2ad8f4f0e0a4dfd1de911.1778176768.git.evvoevod@tenstorrent.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "5d248a013281ea80be3375cfc19e8ca541d33c34", "tree": "b586ee05bcd7ba1a967535a971509b79a1bb99ed", "parents": [ "2257e9957103aac7df8089a59b9d4bdda7c592ce" ], "author": { "name": "Evgeny Voevodin", "email": "evvoevod@tenstorrent.com", "time": "Thu May 07 18:08:02 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat May 09 12:59:43 2026 +0530" }, "message": "include: sbi_scratch: Add tmp1 scratch space for RNMI context saving\n\nRNMI handlers use MNSCRATCH instead of MSCRATCH and need separate scratch\nspace from regular trap handling. Add tmp1 for RNMI context while tmp0\nremains for regular traps.\n\nSigned-off-by: Evgeny Voevodin \u003cevvoevod@tenstorrent.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/0a5d241fa1db03e71a3f56be24708cbbc8037e28.1778176768.git.evvoevod@tenstorrent.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2257e9957103aac7df8089a59b9d4bdda7c592ce", "tree": "eaa7d764db68e5ce43bad271f75448d903ba2232", "parents": [ "ff7d245b86daa36aa36147022fa583e79ffe25cc" ], "author": { "name": "Yu-Chien Peter Lin", "email": "peter.lin@sifive.com", "time": "Wed Mar 11 20:51:16 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Apr 08 17:58:06 2026 +0530" }, "message": "lib: sbi_bitmap_test: add tests for bitmap_empty()\n\nAdd tests for bitmap_empty(), covers empty/non-empty bitmaps and\nedge case nbits\u003d0.\n\nSigned-off-by: Yu-Chien Peter Lin \u003cpeter.lin@sifive.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260311125116.1401002-2-peter.lin@sifive.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ff7d245b86daa36aa36147022fa583e79ffe25cc", "tree": "a713aeb93bbfccce15a2074f5be3f3d92874da29", "parents": [ "0b041e58c0787f76325da5081e41a13bf304d328" ], "author": { "name": "Yu-Chien Peter Lin", "email": "peter.lin@sifive.com", "time": "Wed Mar 11 20:51:15 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Apr 08 17:58:05 2026 +0530" }, "message": "include: sbi_bitmap: add bitmap_empty() function\n\nAdd bitmap_empty() to check if bitmap has no bits set.\n\nUnlike bitmap_weight() which calls sbi_popcount() on every word,\nbitmap_empty() uses simple non-zero comparisons with early exit.\n\nSigned-off-by: Yu-Chien Peter Lin \u003cpeter.lin@sifive.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260311125116.1401002-1-peter.lin@sifive.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "0b041e58c0787f76325da5081e41a13bf304d328", "tree": "f760e8ec16deb744945120e1cc53a2c58efaa6a6", "parents": [ "2bf0de88c8897ff4be5b89c04115c17421ad5687" ], "author": { "name": "Ranbir Singh", "email": "ranbir.singh@oss.qualcomm.com", "time": "Wed Feb 25 11:43:47 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Apr 06 18:23:25 2026 +0530" }, "message": "lib: utils: Add MPXY client driver for RPMI MM service group\n\nAdd necessary infra for implementing RPMI Management Mode\nservice group on platform microcontroller.\n\nCo-authored-by: Sunil V L \u003csunilvl@oss.qualcomm.com\u003e\nSigned-off-by: Ranbir Singh \u003cranbir.singh@oss.qualcomm.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2bf0de88c8897ff4be5b89c04115c17421ad5687", "tree": "8d503dc1c9ff16fc83aa0dbc056bcb2489d1df93", "parents": [ "fdb78b0ec585a318ae6199c7129be389bf78091c" ], "author": { "name": "Chen Pei", "email": "cp0613@linux.alibaba.com", "time": "Fri Mar 06 17:44:25 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Apr 06 17:53:33 2026 +0530" }, "message": "lib: Fix sbi_strchr to correctly handle null terminator search\n\nThe original sbi_strchr implementation did not conform to the C standard\nbehavior. According to the C standard and POSIX specification, strchr(s, 0)\nshould return a pointer to the null terminator at the end of string s.\n\nThe previous implementation used a while loop that would terminate when\neither reaching the end of string or finding the character, but it would\nreturn NULL when searching for the null terminator instead of returning\na pointer to the null terminator itself.\n\nThe fixed implementation uses a do-while loop that ensures even when\nsearching for the null terminator, the function correctly returns a\npointer to the null terminator position rather than NULL.\n\nThis fix ensures sbi_strchr behavior aligns with standard library\nfunction semantics, making it more predictable and safe for users\nexpecting standard C library behavior.\n\nSigned-off-by: Chen Pei \u003ccp0613@linux.alibaba.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260306094425.1918-3-cp0613@linux.alibaba.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "fdb78b0ec585a318ae6199c7129be389bf78091c", "tree": "2f6290d138eb79ff2143d6c59a2982b17c391644", "parents": [ "9e14e03032c3e61658c0e8bf6026e33c777ca0a4" ], "author": { "name": "Chen Pei", "email": "cp0613@linux.alibaba.com", "time": "Fri Mar 06 17:44:24 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Apr 06 17:53:33 2026 +0530" }, "message": "lib: tests: Add test for string\n\nAdded unit tests for various string operations using SBI unit\ntest framework.\n\nSigned-off-by: Chen Pei \u003ccp0613@linux.alibaba.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260306094425.1918-2-cp0613@linux.alibaba.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "9e14e03032c3e61658c0e8bf6026e33c777ca0a4", "tree": "e64b65b0db58cc9b0dfd76316d5c1ed1cebfcb99", "parents": [ "0402b8e3dce9ac71d1c0951cf9716f88ba8dccfc" ], "author": { "name": "Yu-Chien Peter Lin", "email": "peter.lin@sifive.com", "time": "Tue Feb 24 11:17:33 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Apr 06 11:04:33 2026 +0530" }, "message": "sifive_dev_platform: Set default MMIO region when SmePMP is enabled\n\nSet a default MMIO region with a single SmePMP entry, which allows us\nto save entries for M-mode only devices. The default entry has M-/S-mode\nshared permission, so system-level resource protection, such as RISC-V\nWorld extension and WorldGuard checker, will be introduced to protect\nM-mode only region access from lower privilege modes.\n\nReviewed-by: Greentime Hu \u003cgreentime.hu@sifive.com\u003e\nReviewed-by: Zong Li \u003czong.li@sifive.com\u003e\nSigned-off-by: Yu-Chien Peter Lin \u003cpeter.lin@sifive.com\u003e\nLink: https://lore.kernel.org/r/20260224031733.3817148-3-peter.lin@sifive.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "0402b8e3dce9ac71d1c0951cf9716f88ba8dccfc", "tree": "9eadf6ae8387ec1b58bfaa2b33952c2412b554d0", "parents": [ "4813a2042096b7860655761aad973723293a552e" ], "author": { "name": "Yu-Chien Peter Lin", "email": "peter.lin@sifive.com", "time": "Tue Feb 24 11:17:31 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Apr 06 10:49:21 2026 +0530" }, "message": "platform: sifive: Add initial support for SiFive development platform\n\nAdd initial platform support for SiFive development platforms\nwith the \"sifive-dev\" compatible string.\n\nReviewed-by: Greentime Hu \u003cgreentime.hu@sifive.com\u003e\nReviewed-by: Zong Li \u003czong.li@sifive.com\u003e\nSigned-off-by: Yu-Chien Peter Lin \u003cpeter.lin@sifive.com\u003e\nLink: https://lore.kernel.org/r/20260224031733.3817148-1-peter.lin@sifive.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "4813a2042096b7860655761aad973723293a552e", "tree": "d1ad3b62c92126c6ccbd7cb6ec62c4c94355fa03", "parents": [ "0ab0c470d5886ce5852c94f16725c990e7f08662" ], "author": { "name": "Yu-Chien Peter Lin", "email": "peter.lin@sifive.com", "time": "Tue Feb 24 11:17:32 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 11:16:33 2026 +0530" }, "message": "lib: sbi_init: Call hart init and timer init before platform early init\n\nTo allow the platform early drivers to use the sbi_timer_mdelay(),\nsbi_timer_udelay() and sbi_hart_has_extension() helpers, reorder the\ninitialization sequence must call sbi_hart_init() and sbi_timer_init()\nprior to sbi_platform_early_init() during both cold and warm boot paths.\n\nReviewed-by: Greentime Hu \u003cgreentime.hu@sifive.com\u003e\nReviewed-by: Zong Li \u003czong.li@sifive.com\u003e\nSigned-off-by: Yu-Chien Peter Lin \u003cpeter.lin@sifive.com\u003e\nLink: https://lore.kernel.org/r/20260224031733.3817148-2-peter.lin@sifive.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "0ab0c470d5886ce5852c94f16725c990e7f08662", "tree": "05d57bfc1a99c39a3072057b48cdae5806ab353e", "parents": [ "e8ebd1fbc615774f0452e74c850a3dbe00b5c80d" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:42 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:55:58 2026 +0530" }, "message": "lib: sbi_irqchip: Allow registering interrupt handlers\n\nTo handle external interrupts in M-mode, the sbi_irqchip framework\nmust allow registering interrupt handlers from device drivers.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "e8ebd1fbc615774f0452e74c850a3dbe00b5c80d", "tree": "effa65550444586c0efa9ece94b3bb069b567e91", "parents": [ "e82d20122dcf97a357053636c1fc6d268bd4db5c" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:41 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:55:08 2026 +0530" }, "message": "lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip device\n\nAllow locating irqchip device instance using a unique 32-bit ID. This\n32-bit unique ID can be set by the irqchip driver at the time of adding\nirqchip device.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "e82d20122dcf97a357053636c1fc6d268bd4db5c", "tree": "70b642a96f7aa9d09ecadacfba8e815e85c4475b", "parents": [ "b55bb4cdcb298c12a316713d6cc7948973c14f9b" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:40 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:55:03 2026 +0530" }, "message": "lib: utils/irqchip: Add unique_id to plic, aplic, and imsic data\n\nAdd a 32-bit unique ID to plic, aplic, and imsic data which can be\nused to differentiate multiple irqchip devices.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b55bb4cdcb298c12a316713d6cc7948973c14f9b", "tree": "c6ff86c0798e3ed42ba15c0e5f033ca529b3853b", "parents": [ "5a300b32d546d226e55361e47d07b1c9171f07c8" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:39 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:53:33 2026 +0530" }, "message": "lib: sbi_irqchip: Support irqchip device targetting subset of harts\n\nIt is possible to have platform where an irqchip device targets\na subset of harts and there are multiple irqchip devices to cover\nall harts.\n\nTo support this scenario:\n1) Add target_harts hartmask to struct sbi_irqchip_device which\n represents the set of harts targetted by the irqchip device\n2) Call warm_init() and process_hwirqs() callbacks of an irqchip\n device on a hart only if irqchip device targets that particular\n hart\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "5a300b32d546d226e55361e47d07b1c9171f07c8", "tree": "7bf83d20da7ff79fac2f2f838a5f183fdf842699", "parents": [ "6d68f3bebd206314a5b194004249524dbc0da075" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:38 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:52:45 2026 +0530" }, "message": "lib: utils/irqchip: Add IDC to hartindex map in struct aplic_data\n\nA platform can have multiple APLICs in direct-mode targetting\ndifferent subset of harts. Add APLIC ID to hartindex map in\nstruct aplic_data to capture the set of harts targeted by a\ngiven APLIC in direct-mode.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "6d68f3bebd206314a5b194004249524dbc0da075", "tree": "6fcbf4d70f18b3bb2fbfb9a662fb848f9738f32a", "parents": [ "2110aab68fd2e33151416c1ca3070fbb79db814c" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:37 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:52:43 2026 +0530" }, "message": "lib: utils/irqchip: Fix context_map init in irqchip_plic_update_context_map()\n\nThe context_map[][] elements should be initialized with negative\nvalue so that context_map does not point to anything for non-existent\nPLIC contexts.\n\nFixes: 69448a079065 (\"lib: utils/irqchip: plic: Provide a hartindex to context map\")\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-4-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2110aab68fd2e33151416c1ca3070fbb79db814c", "tree": "a718e5a826f80dffb55f65f1174e050f2ddcf232", "parents": [ "51837c731b017bd59b91963aba1dc13691ac07dd" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:36 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:52:41 2026 +0530" }, "message": "lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()\n\nThe irq_handle() callback of irqchip device is meant to process\nhardware interrupt of the irqchip hence rename it accordingly.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "51837c731b017bd59b91963aba1dc13691ac07dd", "tree": "d8616593eb2995786726f00b25bad9503f7a6974", "parents": [ "6d5b2b9b056826e072c387a068e3f8e6700b5cae" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Fri Feb 13 11:23:35 2026 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Mar 22 10:52:40 2026 +0530" }, "message": "lib: sbi_irqchip: Use chip as variable name for irqchip device\n\nThe irqchip device represents an interrupt controller so use chip\nas variable name instead of dev. This will avoid confusion as the\nsbi_irqchip framework grows.\n\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20260213055342.3124872-2-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "6d5b2b9b056826e072c387a068e3f8e6700b5cae", "tree": "08356786163940632749917a991fc3fff3a3ccfd", "parents": [ "b5348006e98077076a0b1a690c3a9f63c7151a4b" ], "author": { "name": "Charlie Jenkins", "email": "thecharlesjenkins@gmail.com", "time": "Mon Mar 02 14:54:58 2026 -0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue Mar 10 13:21:29 2026 +0530" }, "message": "lib: sbi: fix sse_event_inject() status setting\n\nsse_event_inject() currently sets all status bits to 1 except for\nSBI_SSE_ATTR_STATUS_PENDING_OFFSET which it sets to zero. Instead of\noverwriting all the values of the status bits, sse_event_inject() is\nonly expected to clear SBI_SSE_ATTR_STATUS_PENDING_OFFSET. Fix\nsse_event_inject() to only do the clearing.\n\nSigned-off-by: Charlie Jenkins \u003cthecharlesjenkins@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260302-event_inject_fix-v1-1-e88952b03aa4@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b5348006e98077076a0b1a690c3a9f63c7151a4b", "tree": "dfc95256cbf58c842295bd763c1ee726de1d3ad9", "parents": [ "ef1ee40e7d9aeca09a7d9a73a990f279a9ec0a9b" ], "author": { "name": "Marti Alonso", "email": "martialonso11@gmail.com", "time": "Sun Mar 01 20:54:21 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue Mar 10 10:47:23 2026 +0530" }, "message": "lib: Use proper add opcode on RV32 with Zalrsc\n\nThe addw opcode is only defined in RV64, which produces 32-bit results.\nOn RV32, the default add opcode already produces 32-bit results.\n\nFixes: 995f226f3f33 (\"lib: Emit lr and sc instructions based on -march flags\")\nSigned-off-by: Marti Alonso \u003cmartialonso11@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ef1ee40e7d9aeca09a7d9a73a990f279a9ec0a9b", "tree": "c03b1b1e9a901671e583f0b76b939bbaaa82f46b", "parents": [ "4dc1b9f7baac61cb49e9f6b58ebea73cbd663500" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Sun Mar 01 16:13:32 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue Mar 10 10:36:48 2026 +0530" }, "message": "platform: generic: mips boston: update \"compatible\"\n\nUse a platform-specific compatible to avoid clashing\nwith CPU compatible\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Conor Dooley \u003cconor.dooley@microchip.com\u003e\nLink: https://lore.kernel.org/r/20260301141332.2941601-1-vladimir.kondratiev@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "4dc1b9f7baac61cb49e9f6b58ebea73cbd663500", "tree": "0473e77d2d291a12ad531993f4ecb7e007234179", "parents": [ "2727c43f8dcef9f6a0c3c117e30d00de145bde11" ], "author": { "name": "Victoriano Morales", "email": "victoriano.morales@openchip.com", "time": "Thu Feb 19 08:34:27 2026 +0000" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Mar 09 13:50:42 2026 +0530" }, "message": "lib: fdt_helper: Removed unnecessary dt parsing check\n\nThe check for the address being different from 0 for the UART, PLIC,\nAPLIC and IMSIC dt nodes is unnnecessary and could skip valid nodes.\n\nSigned-off-by: Victoriano Morales \u003cvictoriano.morales@openchip.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260219083423.30690-1-victoriano.morales@openchip.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2727c43f8dcef9f6a0c3c117e30d00de145bde11", "tree": "a5abaea0e3db3b0c9b763d3f113f930eaa90ebbe", "parents": [ "3baca10015393359ec46a2500c8ebe7daa9672c6" ], "author": { "name": "Marcos Oduardo", "email": "marcos.oduardo@gmail.com", "time": "Mon Feb 23 01:11:59 2026 +0100" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Mar 09 12:13:20 2026 +0530" }, "message": "lib: sbi: Fix undefined behavior in signed shifts in sbi_hart.c\n\nUBSan detected undefined behavior in sbi_hart.c and sbi_fwft.c (in\nthe case of sbi_fwft.c, the bug comes from a macro call defined at\nsbi_ecall_interface.h) caused by shifting a signed integer into the\nsign bit (1 \u003c\u003c 31)\n\nThis can be fixed by using the 1UL literal, ensuring defined arithmetic.\n\nPlease let me know if there’s any other most suitable solution for\nthis bug.\n\nSigned-off-by: Marcos Oduardo \u003cmarcos.oduardo@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223001202.284612-1-marcos.oduardo@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "3baca10015393359ec46a2500c8ebe7daa9672c6", "tree": "4b4829e3533d61ab862e0b1ca7e9b0e028554b88", "parents": [ "8d1c21b38752301fc6c727eece45c15c663649b0" ], "author": { "name": "Marcos Oduardo", "email": "marcos.oduardo@gmail.com", "time": "Mon Feb 23 00:51:50 2026 +0100" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Mar 09 12:11:24 2026 +0530" }, "message": "include: sbi: Fix illegal shift in sbi_domain.h\n\nIn sbi_domain.h, when checking if a memory region is a subset of\nanother, an undefined behavior arithmetic operation was caught\nwhen sanitizing with UBSan (shift exponent __riscv_xlen).\n\nThis patch adds a check to handle the case where the region order\nis __riscv_xlen, avoiding the illegal shift and ensuring the operation\nremains defined.\n\nPlease let me know if there’s any other most suitable solution for\nthis bug.\n\nSigned-off-by: Marcos Oduardo \u003cmarcos.oduardo@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260222235219.276432-1-marcos.oduardo@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "8d1c21b38752301fc6c727eece45c15c663649b0", "tree": "b5f198feb6075f421c27ed883281c50725b61f7d", "parents": [ "f07be546e5ec992fe7c766491a5403c8bc864ceb" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:55:02 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: eyeq7h: enable ECC on L1 cache\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-23-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "f07be546e5ec992fe7c766491a5403c8bc864ceb", "tree": "7f04f8d6f982b5de318e496665d095e7cb3d0a5e", "parents": [ "331dae1bc184986038fba62504bb129563f53143" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:55:01 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: p8700: fix MIPS specific CSRs\n\nP8700 has MIPS specific CSRs. Fix the list, adding\nfew missing ones and remove few non-existing\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-22-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "331dae1bc184986038fba62504bb129563f53143", "tree": "e0a04ab9105d9bfc7275c06992c960624297307e", "parents": [ "3b55e5c7224f81fef04d2f3139b2bebb542ad1a4" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:55:00 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips eyeq7h: prohibit accessing memory beyond DRAM\n\nSBI code arranges domain PMP regions in a way that last entry is\nall-inclusive \"0..~0 RWX\" and the rest of entries are not programmed.\nThis causes a problem for the eyeq7h.\n\nCPU can issue speculative prefetches to non-existent addresses. If this\naccess goes to the system NOC, it is mis-interpreted as an access\nviolation and error is reported, forcing system reset.\n\nTo prevent such a speculative transaction to leave a CPU cluster,\nblock it using PMP, by restricting memory region to physically present\nmemory. To achieve this, on early init:\n\n- update flags for the last all-inclusive \"0..~0 RWX\" entry to be\n inaccessible MMIO. MMIO serves to set up PMA attributes to uncached\n non-prefetchable, preventing transactions to reach system NOC\n- add an all-permissive entry matching DRAM.\n\nResulting memory regions:\n\nDomain0 Region00 : 0x0000000800100000-0x000000080013ffff M: (F,R,X) S/U: ()\nDomain0 Region01 : 0x0000000800100000-0x00000008001fffff M: (F,R,W) S/U: ()\nDomain0 Region02 : 0x0000000048700000-0x000000004870ffff M: (I,R,W) S/U: ()\nDomain0 Region03 : 0x0000000067480000-0x000000006748ffff M: (I,R,W) S/U: ()\nDomain0 Region04 : 0x0000000067500000-0x000000006750ffff M: (I,R,W) S/U: ()\nDomain0 Region05 : 0x0000000048740000-0x000000004875ffff M: (I,R,W) S/U: ()\nDomain0 Region06 : 0x00000000674c0000-0x00000000674dffff M: (I,R,W) S/U: ()\nDomain0 Region07 : 0x0000000067540000-0x000000006755ffff M: (I,R,W) S/U: ()\nDomain0 Region08 : 0x0000000000000000-0x000000007fffffff M: (I,R,W) S/U: (R,W)\nDomain0 Region09 : 0x0000000800000000-0x00000008ffffffff M: () S/U: (R,W,X)\nDomain0 Region10 : 0x0000001000000000-0x0000001fffffffff M: (I) S/U: (R,W)\nDomain0 Region11 : 0x0000000000000000-0xffffffffffffffff M: (I) S/U: ()\n\nHere Region09 covers DRAM, region 11 set to non-accessible\nuncached no-prefetch for the entire address range\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-21-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "3b55e5c7224f81fef04d2f3139b2bebb542ad1a4", "tree": "892a6e818761a1d5f8328c6e5bb565b2f21bf55d", "parents": [ "9169290ca9f17bc64df20139526831367ecaf26c" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:59 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: dump MMIO regions\n\nDebug print MMIO regions\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-20-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "9169290ca9f17bc64df20139526831367ecaf26c", "tree": "ad8817b0cffb67d4573d7b04f5b0cee6daf27467", "parents": [ "2ca2e0caf081ca1bbab8bf42d645268a95ad72e2" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:58 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2\n\nCPU clusters 1 and 2 cannot access NCORE registers through AUX ports.\nAUX ports of clusters 1 and 2 are connected to NCORE through east port.\nEast port has no access to NCORE registers address space.\n\nRe-route NCORE registers range to MEM port by re-configuring MMIO\nregions in the GCR. REsulting map is as below. Mind a gap between\nregions [1] and [2]; this gap covering NCORE registers now routed\nto the default MEM port\nCluster 0: 4 MMIO regions\n [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA\n [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY\n [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA\n [3] : --disabled--\nCluster 1: 4 MMIO regions\n [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA\n [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY\n [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA\n [3] : --disabled--\nCluster 2: 4 MMIO regions\n [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA\n [1] : 0x0000000020000000-0x00000000677f0000 AUX0 ANY\n [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA\n [3] : --disabled--\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-19-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2ca2e0caf081ca1bbab8bf42d645268a95ad72e2", "tree": "b1d6cc89dcc6579326ea918cc3e9a8a23e093aa6", "parents": [ "a3aeef7c14bd3fd3b67379e84f5a954d59554df4" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:57 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips eyeq7h: synchronize timers across clusters\n\nUse eyeq7 specific method to synchronously restart architectural\nmtimer and eyeq7h specific high-resolution timer with common\nhardware trigger. This ensures all timers are precisely in sync\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-18-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "a3aeef7c14bd3fd3b67379e84f5a954d59554df4", "tree": "c4896e4885bd18edce24ced51677d50faad7a482", "parents": [ "76ecd8f37a97094c51d10a98cb04002aa2aac674" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:56 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: synchronize hi-res timers\n\nThere\u0027s high-resolution (1GHz) timer found in the p8700 cluster.\nThis timer used for precise time measurement by platform specific\nsoftware.\n\nSynchronize this proprietary timers to reference in cluster 0.\nProcedure borrowed from the aclint mtimer.\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-17-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "76ecd8f37a97094c51d10a98cb04002aa2aac674", "tree": "34cba73e3844f380abefbc9eb49c826fd54e0543", "parents": [ "bdec42307472f86f523db6414eb8ab4cae415561" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:55 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: use SBI bitfield manipulator macros\n\nSwitch to GENMASK, EXTRACT_BITFIELD, INSERT_BITFIELD\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-16-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "bdec42307472f86f523db6414eb8ab4cae415561", "tree": "8872efed3df4eb843401fab95f836593debf4547", "parents": [ "df7bbe7c2e43d1e2a1cfb0a9d722d93d66e15694" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:54 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: CPU clusters memranges\n\nReserve memory regions for CPU clusters according to P8700\ncluster memory layout.\n\nThere\u0027s a set of components in the CPU cluster according to [1]\n\n[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "df7bbe7c2e43d1e2a1cfb0a9d722d93d66e15694", "tree": "7a7ef7b9e29adc676ecf48e46765162108801abb", "parents": [ "8935f79c95f14569e018cebe87f70c7e9df9db21" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:53 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: cache geometry detection\n\nP8700 has a read-only cache configuration registers.\nProvide a CPU specific function to extract cache information.\nUse this information in the eyeq7h board for informational\nmessage\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-14-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "8935f79c95f14569e018cebe87f70c7e9df9db21", "tree": "7567e19e39709bb0814402a9584af5e2509910d8", "parents": [ "ee553291d80ffe0f24481cb43ea2a047aad3ef90" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:52 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips eyeq7h: deassert accelerator cluster resets\n\nOn the EyeQ7H board, there\u0027s cluster level resets found in the\naccelerator OLBs. These resets should be deasserted once on boot\nand never used after\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-13-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ee553291d80ffe0f24481cb43ea2a047aad3ef90", "tree": "62c6460ae92f322143a4f57eed3159e5cc7fcbfc", "parents": [ "26748d7e12f55eedc3c667066089c514f89f8b84" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:51 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips eyeq7h: detect accelerators cluster presence\n\nIn the design, accelerator clusters ACC[01] and XNN[01] presence\nindicated by the OLB_WEST register OLB_WEST_TSTCSR.\n\nIn the simulation environments, part (or all) accelerators may be\nnot instantiated\n\nDisable clusters not present in the model, updating the DTB\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-12-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "26748d7e12f55eedc3c667066089c514f89f8b84", "tree": "2ce5e269d3c4ed2e7ff9335d5c5f9a49d48c9991", "parents": [ "79dfc3a86883e3e1a5ebac96144849ae26adc817" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:50 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips eyeq7h: power up clusters with OLB\n\nIn the eyeq7h platform, there\u0027s extra power control for the CPU\nclusters. To enable cluster, it should be powered up using this OLB\nregisters prior to accessing any cluster management registers\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-11-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "79dfc3a86883e3e1a5ebac96144849ae26adc817", "tree": "804474de57ebf95e7d388033a5f7c9b8cf2e459f", "parents": [ "fe82238d291e43e3b688ee3ec2922f6424c4ad45" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:49 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips: add P8700 based \"eyeq7h\" and \"boston\"\n\nRefactor MIPS P8700 support, convert P8700 into a \"CPU\" and add\n2 platforms using this CPU:\n- \"boston\" - FPGA platform developed by MIPS\n- \"eyeq7h\" - automotive platform by Mobileye\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "fe82238d291e43e3b688ee3ec2922f6424c4ad45", "tree": "e89f3ff1cab32dbee13c761e81a71013aa82c54c", "parents": [ "bc2722b0f39a82113e32d336b6cddd60a8f6a85e" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:48 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: access CM registers via match data\n\nModify the coherence manager register accessors to use the global variable\np8700_cm_info instead of the statically declared GLOBAL_CM_BASE array.\n\nAlso use p8700_cm_info to get the number of coherence managers and their\nbase addresses in mips_p8700_early_init() and mips_p8700_nascent_init().\n\nClean up the hard-coded values in mips/board.h, access to the coherence\nmanager is now fully based on information provided by platform compatible\nfrom the device tree.\n\nSigned-off-by: Benoît Monin \u003cbenoit.monin@bootlin.com\u003e\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-9-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "bc2722b0f39a82113e32d336b6cddd60a8f6a85e", "tree": "b3e3e2d2eddfc7d2f3db24404ebd5d7a81cf1e8f", "parents": [ "c69c159bd033f5b539c810f12fa9a6e523a05709" ], "author": { "name": "Benoît Monin", "email": "benoit.monin@bootlin.com", "time": "Mon Feb 23 16:54:47 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: Add match data for CM info\n\nIntroduce a structure p8700_cm_info holding the number of coherence\nmanagers and their base addresses found in a particular SoC.\n\nDeclare a global pointer to the structure that is set in\nmips_p8700_platform_init(), based on the match data of the platform\ncompatible.\n\nFor the match data of the MIPS P8700, a single coherence manager with\na base address of 0x16100000 is declared, identical to what is found\nin mips/board.h.\n\nFor now, access to the coherence manager register is still based on\nthe hard-coded values defined in mips/board.h.\n\nSigned-off-by: Benoît Monin \u003cbenoit.monin@bootlin.com\u003e\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-8-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "c69c159bd033f5b539c810f12fa9a6e523a05709", "tree": "fcf0d69f82dbe8e798fcc351b77d716aa882956e", "parents": [ "52ac3de50c164c1d3cf4099e949cd818e1145440" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:46 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: use global CM addresses\n\nIn the multi-cluster system each cluster has its own CM (Coherency Manager).\nEvery CM has its \"global\" memory address where it is accessible from\nany bus master.\nInitially, all CMs accessible from the local cluster using same \"local\"\naddress. Transactions by local address are not routed through system bus\nand thus are faster.\n\nRemap CM in every cluster to the local address matching its global address.\nThen, every CM is always accessed using same address, but when transaction\ninitiated from the local cluster it is routed internally.\n\nThis removes need for 2 PMP regions covering local address access.\nCM accessor functions simplified because there\u0027s no need to detect whether\ntransaction is local or global\n\nAccess timer always in cluster 0\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "52ac3de50c164c1d3cf4099e949cd818e1145440", "tree": "ee0c34ae732b58f2171cdac2412e15781c34214e", "parents": [ "6545b78bcd82dabf07a14c65fce32e6fcd85394b" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:45 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: faster core boot\n\nWhen powering up cores, wait for power up to complete\nusing tight loop. This saves 10ms delay observed for every core\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-6-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "6545b78bcd82dabf07a14c65fce32e6fcd85394b", "tree": "a3ee082a480b46ac5b0c7d27a032a2822a0242c6", "parents": [ "698ea046e25c93b63d1688eb303e9fdcc2767172" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:44 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: fix powering up other cluster\n\nWhile powering up cluster, only indication is bit in cluster\npower control.\n\nIt used to wait for CORE0 in that cluster reach U5 state\n(non-coherent execution), this won\u0027t happen when only CM\npowered up without booting any core\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-5-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "698ea046e25c93b63d1688eb303e9fdcc2767172", "tree": "c624f56962467f1139dfc226e1d020af49bed4a1", "parents": [ "d2dd699add0b90782dffee742ed1854f9b1532ad" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:43 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: reserve memory for M-mode peripherals\n\nReserve memory upfront in large well aligned chunks,\nto avoid problem with PMP granularity that is\n64Kbytes for the p8700 CPU\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-4-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "d2dd699add0b90782dffee742ed1854f9b1532ad", "tree": "c7bba9e6210b9d8ed91abec757913908ea0760d4", "parents": [ "ea45923765de4145d174b98abc6b945c8407265e" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:42 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "platform: generic: mips p8700: improve CM access tracing\n\nuse function call like format; debug print returning value\nof the \"read\" accessor\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-3-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ea45923765de4145d174b98abc6b945c8407265e", "tree": "2841457668d35ef32d51105236a1c16be8cdc5c6", "parents": [ "e58d5287020a4a474a6d04c7bcab800825d1a294" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:41 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "lib: sbi_hart_pmp: disable unconfigured PMP entries\n\nDisable PMP entries not configured in domain. These entries\nmay contain values configured by the boot loader; disabling it\nto be certain PMP configuration is exactly as configured by the\nopenSBI\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-2-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "e58d5287020a4a474a6d04c7bcab800825d1a294", "tree": "e228c6401c15b15751a3d62869778bbfda81b5fc", "parents": [ "9656943bd3a2cad9418465c2a168f907ea52189b" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Feb 23 16:54:40 2026 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 25 18:49:03 2026 +0530" }, "message": "lib: sbi: print hartid in hex\n\nHartid is better represented by hex number since it is likely\na combination of bits representing various elements in the\nplatform hierarchy\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-1-621d004d1a21@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "9656943bd3a2cad9418465c2a168f907ea52189b", "tree": "04725beb8948ac656fde960c707f1b3b54f0949a", "parents": [ "a95c36f16566213c5c58937b1f1b0c8209e60dbd" ], "author": { "name": "James Raphael Tiovalen", "email": "jamestiotio@gmail.com", "time": "Sun Jan 25 17:06:43 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat Feb 21 10:20:41 2026 +0530" }, "message": "lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64\n\nCurrently, when we attempt to read the upper 32 bits of a firmware\ncounter on RV64 or higher, we just set `sbiret.value` to 0 without\nvalidating the counter index. The SBI specification requires us to set\n`sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to\na hardware counter or an invalid counter. Add a validation check to\nensure compliance with the specification on RV64 or higher.\n\nFixes: 51951d9e9af8 (\"lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi\")\nSigned-off-by: James Raphael Tiovalen \u003cjamestiotio@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260125090643.190748-1-jamestiotio@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "a95c36f16566213c5c58937b1f1b0c8209e60dbd", "tree": "82fd69a64f6b91e16dcf642fbdd0e171bcb090ba", "parents": [ "b07e449d15c534407391cb7b430117fefed084af" ], "author": { "name": "James Raphael Tiovalen", "email": "jamestiotio@gmail.com", "time": "Sat Jan 17 00:53:04 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Fri Feb 20 17:24:55 2026 +0530" }, "message": "lib: sbi_pmu: Fix multiple FW counter start operations with custom PMU device\n\nCurrently, we immediately return the result of `fw_counter_start` if the\nevent code is 0xFFFF. However, this skips setting the bit in the\n`fw_counters_started` bitmap even if the platform-specific call\nsucceeds. Restore the original behavior of returning early only on an\nerror so that we still set the bit in the bitmap. This prevents multiple\nstarts of the same FW counter. This also aligns the expectations of\n`pmu_ctr_start_fw` with `pmu_ctr_stop_fw` since we cannot assume that\nthe platform-specific functions to start and stop FW counters will\nmodify the bitmap state.\n\nFixes: 57d3aa3b0dbd (\"lib: sbi_pmu: Introduce fw_counter_write_value API\")\nSigned-off-by: James Raphael Tiovalen \u003cjamestiotio@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260116165304.180441-1-jamestiotio@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b07e449d15c534407391cb7b430117fefed084af", "tree": "270c9e9ddb593c435a171d7afc43d1566c7f787f", "parents": [ "ecdb6c90c83dfc89964e55d7c2a94a5c0f6bc437" ], "author": { "name": "Icenowy Zheng", "email": "zhengxingda@iscas.ac.cn", "time": "Sun Jan 04 14:55:06 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Fri Feb 20 16:50:35 2026 +0530" }, "message": "lib: utils/serial: Add support for Altera JTAG UART\n\nAltera provides a JTAG UART core that provides virtual UART over JTAG\nand can coexist with their virtual JTAG. [1] This core has already been\nsupported by Linux and the programming interface has always been stable.\n\nAdd support for it to OpenSBI to ease JTAG prototype bringing up.\n\nThe driver follows the device tree binding in mainline Linux. [2]\n\n[1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core\n[2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml\n\nSigned-off-by: Icenowy Zheng \u003czhengxingda@iscas.ac.cn\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ecdb6c90c83dfc89964e55d7c2a94a5c0f6bc437", "tree": "047981e153e6123c8f970d6b17f297062cafa7ee", "parents": [ "b27ecec76b8acfece9c28078d02cbc6bc762135c" ], "author": { "name": "Xiang W", "email": "wxjstz@126.com", "time": "Sun Jan 04 13:18:10 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Fri Feb 20 11:23:13 2026 +0530" }, "message": "firmware: Initialize stack guard via Zkr\n\nTry to initialize stack protection guard via the zkr extension.\n\nSigned-off-by: Xiang W \u003cwxjstz@126.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260104051812.128496-1-wxjstz@126.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "b27ecec76b8acfece9c28078d02cbc6bc762135c", "tree": "4f792d1fff8cc1f21db663e02a048db3d658cbce", "parents": [ "82b0961821e45768a91139b8ec5d7784586aa7f9" ], "author": { "name": "Ben Zong-You Xie", "email": "ben717@andestech.com", "time": "Mon Dec 29 15:19:14 2025 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 11 12:14:04 2026 +0530" }, "message": "lib: utils/suspend: add Andes ATCSMU suspend driver\n\nImplement a system-wide suspend driver for the Andes AE350 platform.\nThis driver supports Andes-specific deep sleep (suspend to RAM) and\nlight sleep (suspend to standby) functionalities via the ATCSMU.\n\nThe major differences between deep sleep and light sleep are:\n\n- Power Domain and Resume Path: Deep sleep powers down the core domain.\n Consequently, harts waking from deep sleep resume from the reset\n vector. Light sleep utilizes clock gating to the core domain; harts\n maintain state and resume execution at the instruction immediately\n following the WFI instruction.\n\n- Primary Hart Wakeup: In both modes, the primary hart is woken by\n UART or RTC alarm interrupts. In deep sleep, the primary hart is\n additionally responsible for re-enabling the Last Level Cache (LLC)\n and restoring Andes-specific CSRs.\n\n- Secondary Hart Wakeup: In light sleep, secondary harts are woken\n by an IPI sent from the primary hart. In deep sleep, they are\n woken by an ATCSMU hardware wake-up command. Furthermore,\n secondary harts must restore Andes-specific CSRs when returning\n from deep sleep.\n\nSigned-off-by: Ben Zong-You Xie \u003cben717@andestech.com\u003e\nSigned-off-by: Leo Yu-Chi Liang \u003cycliang@andestech.com\u003e\nLink: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "82b0961821e45768a91139b8ec5d7784586aa7f9", "tree": "35a635661eb8e7c35b0fb9a8f4611939766014c5", "parents": [ "6d26b43c477a7616d1f030261430127fa6c61d27" ], "author": { "name": "Ben Zong-You Xie", "email": "ben717@andestech.com", "time": "Mon Dec 29 15:19:13 2025 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 11 12:13:01 2026 +0530" }, "message": "lib: utils/cache: add Andes last level cache controller\n\nIntroduce a FDT-based driver for the Andes Last Level Cache (LLC)\ncontroller to support cache maintenance operations.\n\nSigned-off-by: Ben Zong-You Xie \u003cben717@andestech.com\u003e\nLink: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "6d26b43c477a7616d1f030261430127fa6c61d27", "tree": "14172ff1a148fbfc4f987b62ff3125b97c0cf806", "parents": [ "85bff9cc163e05130899264eb6e963fc582de117" ], "author": { "name": "Ben Zong-You Xie", "email": "ben717@andestech.com", "time": "Mon Dec 29 15:19:12 2025 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 11 12:11:06 2026 +0530" }, "message": "lib: utils/cache: add cache enable function\n\nAdd functions to enable/disable the cache.\n\nSigned-off-by: Ben Zong-You Xie \u003cben717@andestech.com\u003e\nLink: https://lore.kernel.org/r/20251229071914.1451587-4-ben717@andestech.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "85bff9cc163e05130899264eb6e963fc582de117", "tree": "aeaf6765355c189f47775570e2259bd2fbe0a06c", "parents": [ "9ffacc8ae1ca07ed36d57f887d62a65ae7a44223" ], "author": { "name": "Ben Zong-You Xie", "email": "ben717@andestech.com", "time": "Mon Dec 29 15:19:11 2025 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 11 12:04:01 2026 +0530" }, "message": "platform: generic/andes: add CSR save and restore functions for AE350 platform\n\nImplement a save and restore mechanism for Andes-specific CSRs to support\nhardware power-saving modes, such as CPU hotplug or suspend to RAM.\n\nSigned-off-by: Ben Zong-You Xie \u003cben717@andestech.com\u003e\nSigned-off-by: Leo Yu-Chi Liang \u003cycliang@andestech.com\u003e\nLink: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "9ffacc8ae1ca07ed36d57f887d62a65ae7a44223", "tree": "5afcb8ec6848672d817dffc27462c5f6f8429357", "parents": [ "74434f255873d74e56cc50aa762d1caf24c099f8" ], "author": { "name": "Ben Zong-You Xie", "email": "ben717@andestech.com", "time": "Mon Dec 29 15:19:10 2025 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Wed Feb 11 12:03:50 2026 +0530" }, "message": "lib: utils/hsm: factor out ATCSMU code into an HSM driver\n\nRefactor ATCSMU (System Management Unit) support by moving it from a\nsystem utility into a dedicated FDT-based HSM driver.\n\nKey changes include:\n\n- Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver\n- Moving hart start and stop operations on AE350 platform into the new\n HSM driver\n- Converting the assembly-based functions in sleep.S to C code for the\n readability\n- Updating the ATCWDT200 driver\n\nSigned-off-by: Ben Zong-You Xie \u003cben717@andestech.com\u003e\nSigned-off-by: Leo Yu-Chi Liang \u003cycliang@andestech.com\u003e\nLink: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "74434f255873d74e56cc50aa762d1caf24c099f8", "tree": "bc73e7678872920c7731e9c08c7f09bb381299a7", "parents": [ "65fac653113bcd1ac86ac85f44138caa69ad3d9a" ], "author": { "name": "Michal Simek", "email": "michal.simek@amd.com", "time": "Wed Jan 07 17:04:56 2026 +0100" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Thu Jan 08 14:18:14 2026 +0530" }, "message": "lib: sbi: Fix behavior on platform without HART protection\n\nThe commit 42139bb9b7dc (\"lib: sbi: Replace sbi_hart_pmp_xyz() and\nsbi_hart_map/unmap_addr()\") changed logic by calling\nsbi_hart_protection_configure(). But when protection doesn\u0027t exist\nthe function is returning SBI_EINVAL.\nBut on systems without protection this is correct configuration\nthat\u0027s why do not hang when system don\u0027t have any HART protection.\n\nFixes: 42139bb9b7dc (\"lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()\")\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/bb8641e5f82654e3989537cea85f165f67a7044e.1767801896.git.michal.simek@amd.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "65fac653113bcd1ac86ac85f44138caa69ad3d9a", "tree": "3b109660a975ba6ef12d5e562e00da321e3c12c8", "parents": [ "e7fa66c2160ec139de1853a00f669c09320a9256" ], "author": { "name": "Leo Yu-Chi Liang", "email": "ycliang@andestech.com", "time": "Wed Jan 07 11:26:02 2026 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Thu Jan 08 12:40:32 2026 +0530" }, "message": "include: sbi_scratch: fix typo sbi_scratch -\u003e HART id\n\nFix \"sbi_scratch\" to \"HART id\" to better reflect its purpose.\n\nSigned-off-by: Leo Yu-Chi Liang \u003cycliang@andestech.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260107032602.1143819-1-ycliang@andestech.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "e7fa66c2160ec139de1853a00f669c09320a9256", "tree": "76de2610bf6cfcba55ce985a469ecaaa7308d351", "parents": [ "9a46ef43a45ee1c462c17a0fa62e03c955911192" ], "author": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Dec 29 12:24:16 2025 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Mon Dec 29 12:24:16 2025 +0530" }, "message": "include: Bump-up version to 1.8\n\nUpdate the OpenSBI version to 1.8 as part of release preparation.\n\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "9a46ef43a45ee1c462c17a0fa62e03c955911192", "tree": "bce10c79b8e78e33cadb819848e2820706e82d65", "parents": [ "f6fa62bd169e55f479b137da13ca83b27bb304a9" ], "author": { "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com", "time": "Sat Dec 27 15:39:16 2025 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Dec 28 20:47:12 2025 +0530" }, "message": "include: Fix LLVM compile error in sbi_utils/hsm/fdt_hsm_sifive_inst.h\n\nCurrently, OpenSBI fails to compile for LLVM\u003d1 using 2025.11.27\nriscv-gnu-toolchain with the following error:\n\nIn file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20:\nopensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:17:23: error: expected instruction format\n 17 | __asm__ __volatile__(\".insn 0xfc000073\" ::: \"memory\");\n | ^\n\u003cinline asm\u003e:1:8: note: instantiated into assembly here\n 1 | .insn 0xfc000073\n | ^\nIn file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20:\nopensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:12:23: error: expected instruction format\n 12 | __asm__ __volatile__(\".insn 0x30500073\" ::: \"memory\");\n | ^\n\u003cinline asm\u003e:1:8: note: instantiated into assembly here\n 1 | .insn 0x30500073\n | ^\n2 errors generated.\n\nTo fix this compile error, use \".word\" in-place \".insn\".\n\nFixes: 1514a327306b (\"lib: utils/hsm: Add SiFive TMC0 driver\")\nSigned-off-by: Anup Patel \u003canup.patel@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/r/20251227100916.327524-1-anup.patel@oss.qualcomm.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "f6fa62bd169e55f479b137da13ca83b27bb304a9", "tree": "31ef2428b6a703114892f89f186b867e555596f3", "parents": [ "4c1c77e085599f6f95df4b94714e1d7829ebefbf" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Sun Dec 28 09:33:21 2025 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Dec 28 20:44:03 2025 +0530" }, "message": "lib: atomics: fix AMO test macros\n\nThe \"RISC-V C API\" [1] defines architecture extension test macros\nsays naming rule for the test macros is __riscv_\u003cext_name\u003e, where\n\u003cext_name\u003e is all lower-case.\n\nThree extensions dealing with atomics implementation are:\n \"zaamo\" consists of AMO instructions,\n \"zalrsc\" - LR/SC,\n \"a\" extension means both \"zaamo\" and \"zalrsc\"\nBuilt-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc.\nAlternative to the __riscv_a macro name, __riscv_atomic, is deprecated.\n\nUse correct test macro __riscv_zaamo for the AMO variant of atomics.\nIt used to be __riscv_atomic that is both deprecated and incorrect\nbecause it tests for the \"a\" extension; i.e. both \"zaamo\" and \"zalrsc\"\nIf ISA enables only zaamo but not zalrsc, code as it was would not compile.\n\nOlder toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so\nquery __riscv_atomic - it should be treated as both __riscv_zaamo and\n__riscv_zalrsc, in all present cases __riscv_zaamo is more favorable\nso take is as alternative for __riscv_zaamo\n\n[1] https://github.com/riscv-non-isa/riscv-c-api-doc\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251228073321.1533844-1-vladimir.kondratiev@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "4c1c77e085599f6f95df4b94714e1d7829ebefbf", "tree": "26d4b8196d334bb2373b92177ec646a281d3be5a", "parents": [ "f7b81034aa4c19199afac6be4e033270f3755bf5" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Mon Dec 15 21:25:28 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat Dec 27 11:21:27 2025 +0530" }, "message": "include: riscv_asm: Optimize csr_xyz() macros to reduce stack usage\n\nWhen using debug builds, aka., DEBUG\u003d1, csr_write_num() function can\ntrigger stack overflow. This is caused by the large amount of macro\nexpansion of csr_write(...), which, under debug builds, will generate\nmassive amount of stack variables (tested with GCC 13.2.0). The issue\nis masked previously as we didn\u0027t have too many csr_write()\u0027s before\ncommit 55296fd27c0c, but now, it does overflow the default 4KB stack.\n\nThe csr_read(relaxed) macros already use the \"register\" modifier to\noptimize stack usage (perhaps unknowingly?), so this patch just\nfollows suit.\n\nFixes: 55296fd27c0c (\"lib: Allow custom CSRs in csr_read_num() and csr_write_num()\")\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251216052528.18896-1-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "f7b81034aa4c19199afac6be4e033270f3755bf5", "tree": "6385207c00ba167953020b35312283ebe9f3ad15", "parents": [ "19f0c8351213466cce5c15fdfe35749362fe3469" ], "author": { "name": "James Raphael Tiovalen", "email": "jamestiotio@gmail.com", "time": "Sat Dec 13 18:41:46 2025 +0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat Dec 27 11:04:43 2025 +0530" }, "message": "lib: sbi_pmu: Fix multiple start and stop operations of FW counters\n\nCurrently, OpenSBI returns SBI_ERR_ALREADY_STARTED when attempting to\nstart a HW counter that is already started and SBI_ERR_ALREADY_STOPPED\nwhen attempting to stop a HW counter that is already stopped. However,\nthis is not yet implemented for FW counters.\n\nAdd the necessary checks to return the same error codes when attempting\nthe same actions on FW counters.\n\nSigned-off-by: James Raphael Tiovalen \u003cjamestiotio@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251213104146.422972-1-jamestiotio@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "19f0c8351213466cce5c15fdfe35749362fe3469", "tree": "2221dd627ad5133040f033c356290610fb215788", "parents": [ "fbb5fe811d453c11dbcacf8cfe2fa7e445834475" ], "author": { "name": "Vladimir Kondratiev", "email": "vladimir.kondratiev@mobileye.com", "time": "Mon Dec 08 14:56:17 2025 +0200" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sat Dec 27 10:42:44 2025 +0530" }, "message": "lib/sbi: optimize domain memory regions copying\n\nThere are 2 locations where memory regions moved in a bulk,\nbut this implemented in a region-by region move or even swap.\n\nUse more effective way. Note, last entry, dom-\u003eregions[count], always\nexists and is empty, copying it replaces clear_region()\n\nSigned-off-by: Vladimir Kondratiev \u003cvladimir.kondratiev@mobileye.com\u003e\nReviewed-by: Samuel Holland \u003csamuel.holland@sifive.com\u003e\nLink: https://lore.kernel.org/r/20251208125617.2557594-1-vladimir.kondratiev@mobileye.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "fbb5fe811d453c11dbcacf8cfe2fa7e445834475", "tree": "e42cbe689da22a1dfcc3f66843c54a4db19167b4", "parents": [ "73183a60ab5d2eead290965b783eb1a170804741" ], "author": { "name": "Deepak Gupta", "email": "debug@rivosinc.com", "time": "Mon Nov 24 14:03:39 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Fri Dec 26 16:22:09 2025 +0530" }, "message": "lib: sbi: expected trap must always clear MPRV\n\nExpected trap must always clear MPRV. Currently it doesn\u0027t. There is a\nsecurity issue here where if firmware was doing ld/st with MPRV\u003d1 and\nsince there would be a expected trap, opensbi will continue to run as\nMPRV\u003d1. Security impact is DoS where opensbi will just keep trapping.\n\nSigned-off-by: Deepak Gupta \u003cdebug@rivosinc.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251124220339.3695940-1-debug@rivosinc.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "73183a60ab5d2eead290965b783eb1a170804741", "tree": "106641a3983257ec8045a02dc6618bc5c38b811d", "parents": [ "fbff3a7e0784a5bd42e87656e6d50cea94dfcff5" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:43 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Dec 21 21:02:46 2025 +0530" }, "message": "platform: generic: eswin: Add shutdown/reboot support for Hifive Premier P550\n\nHifive Premier P550[1] is a Mini-DTX form factor board with EIC7700X.\nIt has a STM32F407VET6 onboard MCU acting as the BMC, controlling\nATX power on/off while providing remote management features. The\nEIC7700X SoC/SoM communicates with the BMC via UART2, using ESWIN\u0027s\nprotocol. The messages transmitted are fixed sizes (267 bytes), and\ndepending on the type, can be directional or bi-directional. The\nshutdown and cold reboot requests are directional messages from SoC\nto BMC (NOTIFY type) with CMD_POWER_OFF or CMD_RESTART. The payload\nof shutdown/cold reboot requests should be empty and are ignored by\nthe BMC at the moment. A HFP (Hifive Premier) specific reset device\nis registered in addition to the SoC reset device. For shutdown and\ncold reboot, the board-level reset takes precedence.\n\nThe definitions of the SoC \u003c-\u003e BMC message protocol is taken from\nESWIN\u0027s repo [2]. The only file used from that repo is `hf_common.h`\nIt\u0027s disjunctively dual licensed as (GPL-2.0-only OR BSD-2-Clause),\nhence, compatible with the license of OpenSBI. It\u0027s heavily modified\nand renamed as platform/generic/include/eswin/hfp.h. The author and\ncopyright in the original file are retained.\n\nValidated shutdown/cold reboot working on Hifive Premier P550.\n\n[1] https://www.sifive.com/boards/hifive-premier-p550#documentation\n[2] https://github.com/eswincomputing/hifive-premier-p550-mcu-patches.git\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-8-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "fbff3a7e0784a5bd42e87656e6d50cea94dfcff5", "tree": "55791bc2f43476d556f6fe143ae385a9b528c794", "parents": [ "e5797e0688c187168ed9632b955cbe68da97f7f7" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:42 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Dec 21 21:02:44 2025 +0530" }, "message": "lib: utils/serial: Support multiple UART8250 devices\n\nPreviously we assume only 1 UART8250 instance can be used. Now we support\nmultiple instances by introducing counterpart functions to putc/getc/init\nwhich take an extra *dev parameter, and name them as uart8250_device_xyz()\nThe original functions without the *dev parameter will operate on the\ndefault instance exactly the same as before, so no changes on the caller\nis required.\n\nNote: uart8250_device_init only does device initialization without the\nconsole registration logic.\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "e5797e0688c187168ed9632b955cbe68da97f7f7", "tree": "ad328cc1873ba1d547e72835462842a3f54da5f1", "parents": [ "878c2676e633ff05a8275c2ff76254990e120bed" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:41 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Sun Dec 21 21:02:22 2025 +0530" }, "message": "platform: generic: eswin: add EIC7700\n\nInitial platform support for ESWIN Computing EIC7700 based on public SoC\ndatasheet[1] and tested on HiFive Premier P550. Vendor U-boot/Linux boots\nfine, and I\u0027ve tested Geekbench 6.5.0 Preview and got scores on par with\nthe vendor OpenSBI. System shutdown/reboot for HiFive Premier P550 and\nother boards will be implemented in subsequent commits. At this point,\nonly SoC-level warm reset is implemented.\n\nThe files and functions are intentionally named as eic770x in many places\nfor future enhancements to support the 2 die version of the same SoC,\nnamely EIC7702, seen on DC-ROMA AI PC FML13V03 [2]. This patch set only\ndeals with the single die version, and the assumption is we can be either\ndie with id\u003d0 or id\u003d1, but there\u0027s only a single die in the system, or we\nare only using a single die out of 2. However, the way the SoC handles 2-\ndie greatly affects how we configure it in a 1-die setup. EIC770X address\nmap has die 0/1 memory regions interleaved (see comments in eic770x.c).\nIf only 1 die is connected or active, it creates holes in the address map\nfor those regions corresponding to the remote die. When speculative-\nexecution or HW prefetcher touches data-cacheable regions that happen to\nfall into those holes, it can trigger bus error. Specifically:\n\n - Remote (non-existent) die L3 zero device\n - Remote (non-existent) die cached memory region\n - Other holes in Memory Port\n\nTo make matters worse, EIC770X doesn\u0027t have cache coherent DMA, and due\nto the fact that the P550 core lacks Svpbmt, the SoC maps main memory\ntwice as different regions, so it can bypass cache and fetch the data\ndirectly from memory. In address space, we have two memory regions, one\nas cached, the other as uncached. Thus, we also need an extra PMP entry\nto protect OpenSBI blob from the uncached window. To do this, platform\ncode requires single_fw_region, otherwise, we\u0027ll run out of PMP entries.\n\nEIC770X also have several feature disable/enable CSRs accessible in M\nmode. By default many core features such as speculation and HW prefetch\nare disabled, and M mode software is responsible of enabling. Hence,\nintroduce 4 new build time tunable parameters to Kconfig, which reflects\nthe values get updated to those CSRs:\n - ESWIN_EIC770X_FEAT0_CFG\n - ESWIN_EIC770X_FEAT1_CFG\n - ESWIN_EIC770X_L1_HWPF_CFG\n - ESWIN_EIC770X_L2_HWPF_CFG\n\nThe default values are somewhat optimal for generic workloads. They are\ndumped when running SiFive\u0027s vendor OpenSBI, and in addition, with my\nown tuning to address the perf regression reported by drmpeg [3]\n\nTo build the firmware+u-boot blob, Use the following, and docs [4] for\ntesting it with UART boot without flashing:\n\nmake FW_TEXT_START\u003d0x80000000 \\\n FW_PAYLOAD_OFFSET\u003d0x200000 \\\n FW_PAYLOAD_PATH\u003du-boot-nodtb.bin \\\n FW_PAYLOAD_FDT_ADDR\u003d0xf8000000 \\\n FW_FDT_PATH\u003du-boot.dtb\n\n[1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual\n[2] https://github.com/geerlingguy/sbc-reviews/issues/82\n[3] https://forums.sifive.com/t/low-1-core-stream-bandwidth/7274/15\n[4] https://github.com/ganboing/EIC770x-Docs/blob/main/p550/bootchain/UART-Boot.md\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-6-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "878c2676e633ff05a8275c2ff76254990e120bed", "tree": "0a5382a9df2d6a30c4913d0c57eb6edb5d19d190", "parents": [ "ed1deab09ef6284d018fbf37ab397dcd4b9f82b8" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:40 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anuppate@hu-anuppate-blr.qualcomm.com", "time": "Sun Dec 21 20:33:23 2025 +0530" }, "message": "lib: sbi: give platform choice of using single memregion to cover OpenSBI\n\nBy default the OpenSBI itself is covered by 2 memregions for RX/RW\nsections. This is required by platforms with Smepmp to enforce\nproper permissions in M mode. Note: M-mode only regions can\u0027t\nhave RWX permissions with Smepmp. Platforms with traditional PMPs\nwon\u0027t be able to benefit from it, as both regions are effectively\nRWX in M mode, but usually it\u0027s harmless to so. Now we provide\nthese platforms with an option to disable this logic. It saves 1\nPMP entry. For platforms really in short of PMPs, it does make a\ndifference.\n\nNote: Platform requesting single OpenSBI memregion must be using\n traditional (old) PMP. We expect the platform code to do\n the right thing.\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-5-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "ed1deab09ef6284d018fbf37ab397dcd4b9f82b8", "tree": "1238387acc46f172f51c69493d75fe77c9490854", "parents": [ "2c1bf5bb73194ca035bcd5ab3fbc6653de3162e1" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:39 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anuppate@hu-anuppate-blr.qualcomm.com", "time": "Sun Dec 21 20:33:20 2025 +0530" }, "message": "lib: sbi_domain: make is_region_subset public\n\nThe helper function is renamed as sbi_domain_memregion_is_subset,\nand made public in header file.\n\nAlso add a convenient helper of sbi_domain_for_each_memregion_idx.\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-4-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "2c1bf5bb73194ca035bcd5ab3fbc6653de3162e1", "tree": "f37d7d0f93c902e571873739c51eefb938e7f897", "parents": [ "707aa3231af8c19779e8ca07a950c3a6b331489a" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:38 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anuppate@hu-anuppate-blr.qualcomm.com", "time": "Sun Dec 21 20:33:18 2025 +0530" }, "message": "lib: sbi_domain: add sbi_domain_get_oldpmp_flags\n\nFactor out logic in `sbi_hart_oldpmp_configure` into function\n`sbi_domain_get_oldpmp_flags`, analogous to `sbi_domain_get_smepmp_flags`.\nPlatform specific hart-protection implementation can now leverage it.\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-3-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "707aa3231af8c19779e8ca07a950c3a6b331489a", "tree": "cd6edff4134ae4aa14529ae7cf49dc236ac91d74", "parents": [ "111738090c6cdf2d852717b3ad15b65e2085d237" ], "author": { "name": "Bo Gan", "email": "ganboing@gmail.com", "time": "Thu Dec 18 02:42:37 2025 -0800" }, "committer": { "name": "Anup Patel", "email": "anuppate@hu-anuppate-blr.qualcomm.com", "time": "Sun Dec 21 20:33:16 2025 +0530" }, "message": "lib: sbi_hart_pmp: make sbi_hart_pmp_fence public\n\nsbi_hart_pmp_fence can now be utilized by other hart-protection\nimplementation.\n\nSigned-off-by: Bo Gan \u003cganboing@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20251218104243.562667-2-ganboing@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "111738090c6cdf2d852717b3ad15b65e2085d237", "tree": "83cf3441941caec45f43c8e0e15253369ab40fe3", "parents": [ "843e916dcab4163e84bab9a22ef2db89ff269979" ], "author": { "name": "Andrew Waterman", "email": "andrew@sifive.com", "time": "Thu Nov 27 16:51:21 2025 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue Dec 16 20:19:21 2025 +0530" }, "message": "lib: sbi: Flush TLBs upon FWFT ADUE change\n\nA clarification has been added to the RISC-V privileged specification\nregarding synchronization requirements when xenvcfg.ADUE changes.\n(Refer, the following commit in the RISC-V Privileged ISA spec\nhttps://github.com/riscv/riscv-isa-manual/commit/4e540263db8ae3a27d132a1752cc0fad222facd8)\n\nAs-per these requirements, the SBI FWFT ADUE implementation must\nflush TLBs upon changes in ADUE state on a hart.\n\nSigned-off-by: Andrew Waterman \u003candrew@sifive.com\u003e\nSigned-off-by: Anup Patel \u003capatel@ventanamicro.com\u003e\nLink: https://lore.kernel.org/r/20251127112121.334023-3-apatel@ventanamicro.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "843e916dcab4163e84bab9a22ef2db89ff269979", "tree": "a97e72eeb6da0756ae755f3b3cb392143d6d5b93", "parents": [ "5eec86eec8ee92f9c7d4211c34fddf794609ed71" ], "author": { "name": "Andrew Waterman", "email": "andrew@sifive.com", "time": "Thu Nov 27 16:51:20 2025 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue Dec 16 20:19:21 2025 +0530" }, "message": "lib: sbi: Expose __sbi_sfence_vma_all() function\n\nThe __sbi_sfence_vma_all() can be shared by different parts of\nOpenSBI so rename __tlb_flush_all() to __sbi_sfence_vma_all()\nand make it global function.\n\nSigned-off-by: Andrew Waterman \u003candrew@sifive.com\u003e\nSigned-off-by: Anup Patel \u003capatel@ventanamicro.com\u003e\nLink: https://lore.kernel.org/r/20251127112121.334023-2-apatel@ventanamicro.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" }, { "commit": "5eec86eec8ee92f9c7d4211c34fddf794609ed71", "tree": "6d731d97f7a413ecb71362b11dd1aab810a2a975", "parents": [ "42139bb9b7dc10dcf5432cc34eb1bf2e233ef359" ], "author": { "name": "Anup Patel", "email": "apatel@ventanamicro.com", "time": "Tue Dec 09 19:22:35 2025 +0530" }, "committer": { "name": "Anup Patel", "email": "anup@brainfault.org", "time": "Tue Dec 16 20:16:47 2025 +0530" }, "message": "lib: sbi: Factor-out PMP programming into separate sources\n\nThe PMP programming is a significant part of sbi_hart.c so factor-out\nthis into separate sources sbi_hart_pmp.c and sbi_hart_pmp.h for better\nmaintainability.\n\nSigned-off-by: Anup Patel \u003capatel@ventanamicro.com\u003e\nLink: https://lore.kernel.org/r/20251209135235.423391-6-apatel@ventanamicro.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n" } ], "next": "42139bb9b7dc10dcf5432cc34eb1bf2e233ef359" }