platform: generic: eyeq7h: enable ECC on L1 cache

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-23-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>

platform/generic/mips/eyeq7h.c

diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c
index f09ec5f..242cbb3 100644
--- a/platform/generic/mips/eyeq7h.c
+++ b/platform/generic/mips/eyeq7h.c
@@ -436,6 +436,8 @@
 	/* Per hart set up */
 	/* Enable AMO and RDTIME illegal instruction exceptions. */
 	csr_set(CSR_MIPSCONFIG6, (1<<2)|(1<<1));
+	/* enable ECC for L1 I/D and FTLB */
+	csr_set(CSR_MIPSERRCTL, MIPSERRCTL_PE);
 
 	return 0;
 }