)]}'
{
  "commit": "8f1a6164f2b81fe08d67c09400d9f7b9019c58df",
  "tree": "ba0e39551f1b63ec97230a5ffd76e1c08767dc8e",
  "parents": [
    "e9797b5e574c87332679a30e542b519c93e650ca"
  ],
  "author": {
    "name": "Nicholas Piggin",
    "email": "npiggin@gmail.com",
    "time": "Thu Apr 30 14:55:22 2026 +1000"
  },
  "committer": {
    "name": "Anup Patel",
    "email": "anup@brainfault.org",
    "time": "Wed Jun 10 13:23:18 2026 +0530"
  },
  "message": "lib: sbi: Add PMP CSR read and write accessors\n\nPMPCFG CSR access is non-trivial as it requires shifting and masking, it\nmakes PMP manipulation code simpler if this basic CSR read/write access is\nabstracted away.\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260430045528.420437-6-npiggin@gmail.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "da1900e9dc0c19073c9805de5038bd96191b8bd9",
      "old_mode": 33188,
      "old_path": "lib/sbi/riscv_asm.c",
      "new_id": "6c1f23447c18da91f11c628f7215009a7a0c1d27",
      "new_mode": 33188,
      "new_path": "lib/sbi/riscv_asm.c"
    }
  ]
}