)]}'
{
  "commit": "73bc794b40fc917feb146afd34970cf44563b561",
  "tree": "859e5f3b7adcd6769a81224e7671fab2fba861db",
  "parents": [
    "243035c565ac22a3d694247bd7fc324743999978"
  ],
  "author": {
    "name": "Zishun Yi",
    "email": "vulab@iscas.ac.cn",
    "time": "Thu Apr 30 02:17:47 2026 +0800"
  },
  "committer": {
    "name": "Anup Patel",
    "email": "anup@brainfault.org",
    "time": "Tue Jun 09 22:12:48 2026 +0530"
  },
  "message": "lib: sbi_domain_context: Flush TLB after SATP mode switch\n\nWhen switching between domains with different satp.MODE values (e.g.\nSv39 to Sv48), the RISC-V ISA permits hardware to use cached translations\nfrom the old virtual-address width if no SFENCE.VMA intervenes. This\nconstrained-unpredictable behavior is clarified in riscv-isa-manual\nPR #2219.\n\nThe hart protection re-configuration will anyway do full SFENCE / HFENCE\nso move the hart protection re-configuration after register context switch\nin switch_to_next_domain_context() to ensure translations from the new\ndomain\u0027s address width are used.\n\nLink: https://github.com/riscv/riscv-isa-manual/pull/2219\nSigned-off-by: Zishun Yi \u003cvulab@iscas.ac.cn\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260429181747.160033-1-vulab@iscas.ac.cn\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fad402a8c1d95fbe4a8f4e0c9b8156dd9db74694",
      "old_mode": 33188,
      "old_path": "lib/sbi/sbi_domain_context.c",
      "new_id": "cc4cc04ddb46e0e596fc2c3ecbe3c14e7ddc65e7",
      "new_mode": 33188,
      "new_path": "lib/sbi/sbi_domain_context.c"
    }
  ]
}