)]}'
{
  "commit": "6ad246a1494807ee91e36ffcf60e4c30bb309d45",
  "tree": "55a808af978e000950dcb01e6cf0fc87b71a641f",
  "parents": [
    "2de7dfb6813facba8e376897290bedb18ef38401"
  ],
  "author": {
    "name": "Benoît Monin",
    "email": "benoit.monin@bootlin.com",
    "time": "Wed Sep 02 17:04:07 2026 +0200"
  },
  "committer": {
    "name": "Anup Patel",
    "email": "anup@brainfault.org",
    "time": "Mon Sep 28 18:06:25 2026 +0530"
  },
  "message": "platform: generic: metanoia/mt2824: configure PMA for DSP memory regions\n\nSet up the memory attribute for the XOR RAM, MRAS memory, and RSC table\nused by the DSPs as non-cacheable and bufferable during final init.\n\nSigned-off-by: Benoît Monin \u003cbenoit.monin@bootlin.com\u003e\nReviewed-by: Anup Patel \u003canup@brainfault.org\u003e\nLink: https://lore.kernel.org/r/20260902-mt2824-pma-v1-1-ada8f836365d@bootlin.com\nSigned-off-by: Anup Patel \u003canup@brainfault.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a34304b93179c0bd5d55fdd2b2f3e7fdaf2ef82a",
      "old_mode": 33188,
      "old_path": "platform/generic/metanoia/mt2824/mt2824.c",
      "new_id": "79641dd7afcfe48084ddca68eab2db147b507c3f",
      "new_mode": 33188,
      "new_path": "platform/generic/metanoia/mt2824/mt2824.c"
    }
  ]
}