commit 20ca19ab0323bb3b162a620008d192e2a56302a2
author Himanshu Chauhan <hchauhan@ventanamicro.com> Tue Jan 09 22:30:14 2024 +0530
committer Anup Patel <anup@brainfault.org> Wed Jan 10 09:43:33 2024 +0530
tree f7a2d7a5261a41c9c1423cb995dcb8ce20c81362
parent b752099da8e37ec9749245fde918e9f7dbd9957e

include: sbi: Add TINFO debug trigger CSR

Add the missing TINFO debug trigger CSR.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

include/sbi/riscv_encoding.h

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index f20df76..e74cc0d 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -686,6 +686,7 @@
 #define CSR_TDATA1			0x7a1
 #define CSR_TDATA2			0x7a2
 #define CSR_TDATA3			0x7a3
+#define CSR_TINFO			0x7a4
 
 /* Debug Mode Registers */
 #define CSR_DCSR			0x7b0