)]}'
{
  "commit": "f5828201ea95dff75f12d2db03dafc68ed03645a",
  "tree": "d5e8b9c210828c2e9f3b27a93633028110a5913f",
  "parents": [
    "a69ad342174ac0e6f82eb7859a2487affc0fa4d5"
  ],
  "author": {
    "name": "Michael Brown",
    "email": "mcb30@ipxe.org",
    "time": "Sun Sep 06 14:30:52 2026 +0100"
  },
  "committer": {
    "name": "Michael Brown",
    "email": "mcb30@ipxe.org",
    "time": "Sun Sep 06 15:13:38 2026 +0100"
  },
  "message": "[librm] Preserve CR0 across virt_call()\n\nClearing the CR0.EM and CR0.TS flags is a prerequisite for using the\nAES-NI instructions for AES hardware acceleration: if CR0.EM is set\nthen the CPU will raise an undefined-instruction exception, and if\nCR0.TS is set then the CPU will raise a device-not-available exception\n(expecting the OS to have installed an exception handler that would\nperform a deferred context switch of the FPU/MMX/SSE registers).\n\nPreserve CR0 across virt_call(), to allow the CR0.EM and CR0.TS flags\nto be modified as needed.\n\nSigned-off-by: Michael Brown \u003cmcb30@ipxe.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "faa5c513e7acc4bfc6090cf7908bb1699fe89b80",
      "old_mode": 33188,
      "old_path": "src/arch/x86/transitions/librm.S",
      "new_id": "c08d544a58eb75662a7e35e983fa2e5f4e90770c",
      "new_mode": 33188,
      "new_path": "src/arch/x86/transitions/librm.S"
    }
  ]
}