)]}'
{
  "commit": "b57bc764a578dab8f4a87f2c084249b079cbd844",
  "tree": "d47384f47fa5aa694afcea1a674c3c29962420b1",
  "parents": [
    "787ed9397e5778c1e9ab3b9ab53206e93e365dfd"
  ],
  "author": {
    "name": "Michael Brown",
    "email": "mcb30@ipxe.org",
    "time": "Sun Sep 06 14:47:56 2026 +0100"
  },
  "committer": {
    "name": "Michael Brown",
    "email": "mcb30@ipxe.org",
    "time": "Sun Sep 06 15:13:38 2026 +0100"
  },
  "message": "[librm] Always disable paging when switching to protected mode\n\nCommit 6143057 (\"[librm] Add support for running in 64-bit long mode\")\ntreated disabling paging on the transition into protected mode as\nsomething that needed to be done as a precaution only in a 64-bit\nbuild, on the assumption that in a 32-bit BIOS system nothing else\nwould be enabling paging.\n\nThe Intel SDM states that setting CR0.PG in real mode (with CR0.PE\nclear) will raise a general-protection exception anyway, and so we\nshould never encounter a situation in which CR0.PG is set at this\npoint.  A review of the bochs source code suggests that it may be\npossible to encounter the combination of CR0.PG set with CR0.PE clear\nin an SVM guest.\n\nErr on the side of paranoia and always disable paging as part of the\ntransition from real mode to protected mode.\n\nSigned-off-by: Michael Brown \u003cmcb30@ipxe.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b65466a5b730323f22caaac06086a386951857e9",
      "old_mode": 33188,
      "old_path": "src/arch/x86/transitions/librm.S",
      "new_id": "19c3d0cfe782fb5213f70cbb97e8b2f93de6213f",
      "new_mode": 33188,
      "new_path": "src/arch/x86/transitions/librm.S"
    }
  ]
}