commit b0a8eabbf4d32d789686c32809750f95986dc7cb
author Michael Brown <mcb30@ipxe.org> Mon Oct 28 11:44:41 2024 +0000
committer Michael Brown <mcb30@ipxe.org> Mon Oct 28 13:55:00 2024 +0000
tree b5fb7387630c65e5ea62545f86a8716dee36e512
parent 74710b8316b40c9e3081c1014813867d4764796b

[riscv] Add support for checking CPU extensions reported via device tree

RISC-V seems to allow for direct discovery of CPU features only from
M-mode (e.g. by setting up a trap handler and then attempting to
access a CSR), with S-mode code expected to read the resulting
constructed ISA description from the device tree.

Add the ability to check for the presence of named extensions listed
in the "riscv,isa" property of the device tree node corresponding to
the boot hart.

Signed-off-by: Michael Brown <mcb30@ipxe.org>