)]}'
{
  "commit": "a69ad342174ac0e6f82eb7859a2487affc0fa4d5",
  "tree": "0f48d2e620ae24ffc258f0c42cecf3d8d5f50ec9",
  "parents": [
    "8f334fd55d1a037c4bb091685a62a339b95425ea"
  ],
  "author": {
    "name": "Michael Brown",
    "email": "mcb30@ipxe.org",
    "time": "Sun Sep 06 14:06:32 2026 +0100"
  },
  "committer": {
    "name": "Michael Brown",
    "email": "mcb30@ipxe.org",
    "time": "Sun Sep 06 15:13:38 2026 +0100"
  },
  "message": "[librm] Preserve CR4 across virt_call() if FXSR is supported\n\nSetting the CR4.OSFXSR flag is a prerequisite for using the AES-NI\ninstructions for AES hardware acceleration: if this flag is not set\nthen the CPU will raise an undefined-instruction exception.\n\nWe currently preserve CR4 across virt_call() only for 64-bit builds,\nsince those will modify CR4 by setting CR4.PAE.  Extend this to\npreserve CR4 across virt_call() if FXSR is supported, to allow the\nCR4.OSFXSR flag to be modified as needed.\n\nSigned-off-by: Michael Brown \u003cmcb30@ipxe.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0a99d603912aff51a341b2e511856756aedf3b62",
      "old_mode": 33188,
      "old_path": "src/arch/x86/transitions/librm.S",
      "new_id": "faa5c513e7acc4bfc6090cf7908bb1699fe89b80",
      "new_mode": 33188,
      "new_path": "src/arch/x86/transitions/librm.S"
    }
  ]
}